scholarly journals An FPGA-Based LOCO-ANS Implementation for Lossless and Near-Lossless Image Compression Using High-Level Synthesis

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2934
Author(s):  
Tobías Alonso ◽  
Gustavo Sutter ◽  
Jorge E. López de Vergara
Keyword(s):  
Hardware Implementation ◽  
Low Complexity ◽  
High Level Synthesis ◽  
Raspberry Pi ◽  
Quality Of Results ◽  
Design Time ◽  
Numeral Systems ◽  
High Level ◽  
Image Compressor

In this work, we present and evaluate a hardware architecture for the LOCO-ANS (Low Complexity Lossless Compression with Asymmetric Numeral Systems) lossless and near-lossless image compressor, which is based on JPEG-LS standard. The design is implemented in two FPGA generations, evaluating its performance for different codec configurations. The tests show that the design is capable of up to 40.5 MPixels/s and 124 MPixels/s per lane for Zynq 7020 and UltraScale+ FPGAs, respectively. Compared to the single thread LOCO-ANS software implementation running in a 1.2 GHz Raspberry Pi 3B, each hardware lane achieves 6.5 times higher throughput, even when implemented in an older and cost-optimized chip like the Zynq 7020. Results are also presented for a lossless only version, which achieves a lower footprint and approximately 50% higher performance than the version that supports both lossless and near-lossless. Interestingly, these great results were obtained applying High-Level Synthesis, describing the coder with C++ code, which tends to establish a trade-off between design time and quality of results. These results show that the algorithm is very suitable for hardware implementation. Moreover, the implemented system is faster and achieves higher compression than the best previously available near-lossless JPEG-LS hardware implementation.

A hardware implementation for real-time lane detection using high-level synthesis

2018 ◽  
Author(s):  
Chanon Khongprasongsiri ◽  
Pinit Kumhom ◽  
Watcharapan Suwansantisuk ◽  
Teerasak Chotikawanid ◽  
Surachate Chumpol ◽  
...  
Keyword(s):  
Real Time ◽  
Hardware Implementation ◽  
Lane Detection ◽  
High Level Synthesis ◽  
High Level

scholarly journals LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

2017 ◽  
Vol 50 ◽  
pp. 26-38 ◽  
Author(s):  
Affaq Qamar ◽  
Fahad Bin Muslim ◽  
Javed Iqbal ◽  
Luciano Lavagno
Keyword(s):  
Hardware Implementation ◽  
High Level Synthesis ◽  
High Level

scholarly journals Power Efficient Rapid Design Space Exploration of Integrated Scheduling and Module Selection in High Level Synthesis

2021 ◽  
Author(s):  
Pallabi Sarkar
Keyword(s):  
Power Consumption ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Optimal Solutions ◽  
Power Efficient ◽  
Pi Method ◽  
High Level

High level Synthesis (HLS) or Electronic System Level (ESL) synthesis requires scheduling algorithms that have strong capability to reach optimal/near-optimal solutions with significant rapidity and greater accuracy. A novel power efficient scheduling approach using ‘PI’ method has been presented in this thesis that reduces the final power consumption of the solution at the expenditure of minimal latency clock cycles. The proposed scheduling approach is based on ‘Priority indicator (PI)’ metric and ‘Intersect Matrix’ topology methods that have a tendency to escape local optimal solutions and thereby reach global solutions. Application of the proposed approach results in even distribution of allocated hardware functional units thereby yielding power efficient scheduling solutions. The two main novel and significant aspects of the thesis are: a) Introduction of ‘Intersect Matrix’ topology with its associated algorithm which is used to check for precedence violation during scheduling b) Introduction of PI method using Priority indicator metric that assists in choosing the highest priority node during each iteration of the scheduling optimization process. Comparative analysis of the proposed approach has been done with an existing design space exploration method for qualitative assessment using proposed ‘Quality Cost Factor (Q- metric)’. This Q-metric is a combination of latency and power consumption values for the solution found, which dictates the quality of the final solutions found in terms of cost for both the proposed and existing approaches. An average improvement of approximately 12 % in quality of final solution and average reduction of 59 % in runtime has been achieved by the proposed approach compared to a current scheduling approach for the DSP benchmarks.

High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits

2005 ◽  
Vol 1 (3) ◽  
pp. 259-272 ◽  
Author(s):  
Xiaoyong Tang ◽  
Tianyi Jiang ◽  
Alex K. Jones ◽  
Prithviraj Banerjee
Keyword(s):  
Low Power ◽  
Hardware Implementation ◽  
High Level Synthesis ◽  
High Level
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