scholarly journals A Countermeasure against DPA on SIMON with an Area-Efficient Structure

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 240 ◽  
Author(s):  
Yuanyuan Zhang ◽  
Ning Wu ◽  
Fang Zhou ◽  
Jinbao Zhang ◽  
Muhammad Yahya
Keyword(s):  
Circuit Design ◽  
Power Analysis ◽  
Fault Injection ◽  
Low Cost ◽  
T Test ◽  
Side Channel ◽  
Cryptographic Algorithms ◽  
Randomization Scheme ◽  
The Cost ◽  
Area Efficient

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, we review and analyze the architecture of SIMON algorithm. Secondly, we prove the threat of DPA attack to SIMON by launching actual DPA attack on SIMON 32/64 circuit. Thirdly, a low-cost power randomization scheme is proposed by combining fault injection with double rate technology, and the corresponding circuit design is implemented. To the best of our knowledge, this is the first scheme that applies the combination of fault injection and double rate technology to the DPA-resistance. Finally, the t-test is used to evaluate the security mechanism of the proposed designs with leakage quantification. Our experimental results show that the proposed design implements DPA-resistance of SIMON algorithm at certain overhead the cost of 47.7% LUTs utilization and 39.6% registers consumption. As compared to threshold implementation and bool mask, the proposed scheme has greater advantages in resource consumption.

scholarly journals Comparing the Cost of Protecting Selected Lightweight Block Ciphers against Differential Power Analysis in Low-Cost FPGAs

Computers ◽  
2018 ◽  
Vol 7 (2) ◽  
pp. 28 ◽  
Author(s):  
William Diehl ◽  
Abubakr Abdulgadir ◽  
Jens-Peter Kaps ◽  
Kris Gaj
Keyword(s):  
Power Analysis ◽  
Low Cost ◽  
Block Ciphers ◽  
Differential Power Analysis ◽  
The Cost

Optical Fault Injection Attacks against Cipher Chip

2014 ◽  
Vol 1044-1045 ◽  
pp. 1498-1502 ◽  
Author(s):  
Hong Sheng Wang ◽  
Dao Gang Ji ◽  
Yang Zhang ◽  
Kai Yan Chen ◽  
Kai Song
Keyword(s):  
Fault Injection ◽  
Side Channel ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Secret Information ◽  
Injection Attacks ◽  
Cryptographic Algorithms ◽  
Fault Injection Attacks

Cipher chips, such as microprocessors, are playing the important role in most cryptosystems, and implementing many public cryptographic algorithms. However, Side channel attacks pose serious threats to Cipher chips. Optical Side channel attack is a new kind of method against cipher chips. Two methods are presented in this paper, which shows how to implement optical fault injection attacks against RSA and AES algorithms running on AT89C52 microchip, and demonstrates how to exploit secret information under attack.

Characteristic Analysis of Side Channel Attacks and Various Power Analysis Attack Techniques

2020 ◽  
pp. 182-195
Author(s):  
Shaminder Kaur ◽  
Balwinder Singh ◽  
Harsimran Jit Kaur
Keyword(s):  
Embedded Systems ◽  
Power Analysis ◽  
Side Channel ◽  
Characteristic Analysis ◽  
Side Channel Attacks ◽  
Design Constraints ◽  
Secure Systems ◽  
Cryptographic Algorithms ◽  
Active Attacks ◽  
Insight Into

Embedded systems have a plethora of security solutions and encryption protocols that can protect them against a multitude of attacks. Hardware engineers infuse lot of time and effort in implementing cryptographic algorithms, keeping the analysis of design constraints into rumination. When it comes to designs in potential hostile environment, engineers face a challenge for building resistance-free embedded systems against attacks called side channel attacks. Therefore, there is a strong need to address issues related to side channel attacks. This chapter will provide an insight into the field of hardware security, and will provide a deep investigation of various types of side channel attacks and better understanding of various power analysis tools, which will further give researchers a vision to build efficient and secure systems in order to thwart attacks. This chapter mainly focuses on passive attacks as compared to active attacks since passive attacks are easy to perform and lot of research is going on these attacks.

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks

2021 ◽  
Vol 26 (5) ◽  
pp. 1-36
Author(s):  
Darshana Jayasinghe ◽  
Aleksandar Ignjatovic ◽  
Roshan Ragel ◽  
Jude Angelo Ambrose ◽  
Sri Parameswaran
Keyword(s):  
Power Analysis ◽  
Fault Injection ◽  
Side Channel ◽  
Aging Effects ◽  
Side Channel Attacks ◽  
Power Analysis Attacks ◽  
Injection Attacks ◽  
Differential Fault Analysis ◽  
Secret Keys ◽  
Fault Injection Attacks

Side channel analysis attacks employ the emanated side channel information to deduce the secret keys from cryptographic implementations by analyzing the power traces during execution or scrutinizing faulty outputs. To be effective, a countermeasure must remove or conceal as many as possible side channels. However, many of the countermeasures against side channel attacks are applied independently. In this article, the authors present a novel countermeasure (referred to as QuadSeal ) against Power Analysis Attacks and Electromagentic Fault Injection Attacks (FIAs), which is an extension of the work proposed in Reference [27]. The proposed solution relies on algorithmically balancing both Hamming distances and Hamming weights (where the bit transitions on the registers and gates are balanced, and the total number of 1s and 0s are balanced) by the use of four identical circuits with differing inputs and modified SubByte tables. By randomly rotating the four encryptions, the system is protected against variations, path imbalances, and aging effects. After generating the ciphertext, the output of each circuit is compared against each other to detect any fault injections or to correct the faulty ciphertext to gain reliability. The proposed countermeasure allows components to be switched off to save power or to run four executions in parallel for high performance when resistance against power analysis attacks is not of high priority, which is not available with the existing countermeasures (except software based where source code can be changed). The proposed countermeasure is implemented for Advanced Encryption Standard (AES) and tested against Correlation Power Analysis and Mutual Information Attacks attacks (for up to a million traces), and none of the secret keys was found even after one million power traces (the unprotected AES circuit is vulnerable for power analysis attacks within 5,000 power traces). A detection circuit (referred to as C-FIA circuit) is operated using the algorithmic redundancy presented in four circuits of QuadSeal to mitigate Electromagnetic Fault Injection Attacks. Using Synopsys PrimeTime, we measured the power dissipation of QuadSeal registers and XOR gates to test the effectiveness of Quadruple balancing methodology. We tested the QuadSeal countermeasure with C-FIA circuit against Differential Fault Analysis Attacks up to one million traces; no bytes of the secret key were found. This is the smallest known circuit that is capable of withstanding power-based side channel attacks when electromagnetic injection attack resistance, process variations, path imbalances, and aging effects are considered.

scholarly journals Shaping the Glitch: Optimizing Voltage Fault Injection Attacks

2019 ◽  
pp. 199-224 ◽  
Author(s):  
Claudio Bozzato ◽  
Riccardo Focardi ◽  
Francesco Palmarini
Keyword(s):  
Power Supply ◽  
Fault Injection ◽  
Low Cost ◽  
Injection Technique ◽  
Side Channel ◽  
Sensitive Data ◽  
Injection Attacks ◽  
Side Channels ◽  
Security Checks ◽  
Fault Injection Attacks

Voltage fault injection is a powerful active side channel attack that modifies the execution-flow of a device by creating disturbances on the power supply line. The attack typically aims at skipping security checks or generating side-channels that gradually leak sensitive data, including the firmware code. In this paper we propose a new voltage fault injection technique that generates fully arbitrary voltage glitch waveforms using off-the-shelf and low cost equipment. To show the effectiveness of our setup, we present new, unpublished firmware extraction attacks on six microcontrollers from three major manufacturers: STMicroelectronics, Texas Instruments and Renesas Electronics that, in 2016 declared a market of $1.5 billion, $800 million and $2.5 billion on units sold, respectively. Among the presented attacks, the most challenging ones exploit multiple vulnerabilities and inject over one million glitches, heavily leveraging on the performance and repeatability of the new proposed technique. We perform a thorough evaluation of arbitrary glitch waveforms by comparing the attack performance against two other major V-FI techniques in the literature. Along a responsible disclosure policy, all the vulnerabilities have been timely reported to the manufacturers.

scholarly journals Analysis and Comparison of Table-based Arithmetic to Boolean Masking

2021 ◽  
pp. 275-297
Author(s):  
Michiel Van Beirendonck ◽  
Jan-Pieter D’Anvers ◽  
Ingrid Verbauwhede
Keyword(s):  
Power Analysis ◽  
Experimental Validation ◽  
Side Channel ◽  
Signature Schemes ◽  
Intermediate Variable ◽  
Conversion Algorithm ◽  
Memory Footprint ◽  
Protection Mechanisms ◽  
The Cost ◽  
Additional Memory

Masking is a popular technique to protect cryptographic implementations against side-channel attacks and comes in several variants including Boolean and arithmetic masking. Some masked implementations require conversion between these two variants, which is increasingly the case for masking of post-quantum encryption and signature schemes. One way to perform Arithmetic to Boolean (A2B) mask conversion is a table-based approach first introduced by Coron and Tchulkine, and later corrected and adapted by Debraize in CHES 2012. In this work, we show both analytically and experimentally that the table-based A2B conversion algorithm proposed by Debraize does not achieve the claimed resistance against differential power analysis due to a non-uniform masking of an intermediate variable. This non-uniformity is hard to find analytically but leads to clear leakage in experimental validation. To address the non-uniform masking issue, we propose two new A2B conversions: one that maintains efficiency at the cost of additional memory and one that trades efficiency for a reduced memory footprint. We give analytical and experimental evidence for their security, and will make their implementations, which are shown to be free from side-channel leakage in 100.000 power traces collected on the ARM Cortex-M4, available online. We conclude that when designing side-channel protection mechanisms, it is of paramount importance to perform both a theoretical analysis and an experimental validation of the method.

scholarly journals CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes

Cryptography ◽  
2021 ◽  
Vol 5 (2) ◽  
pp. 13
Author(s):  
Ehsan Aerabi ◽  
David Hély ◽  
Cyril Bresch ◽  
Athanasios Papadimitriou ◽  
Mahdi Fazeli
Keyword(s):  
Power Analysis ◽  
High Performance ◽  
Fault Injection ◽  
Signal To Noise Ratio ◽  
Side Channel ◽  
Testing Methods ◽  
Signal To Noise ◽  
Correlation Power Analysis ◽  
Variance Testing

CONFISCA is the first generic SIMD-based software countermeasure that can concurrently resist against Side-Channel Attack (SCA) and Fault Injection (FI). Its promising strength is presented in a PRESENT cipher case study and compared to software-based Dual-rail with Pre-charge Logic concurrent countermeasure. It has lower overhead, wider usability, and higher protection. Its protection has been compared using Correlation Power Analysis, Welch’s T-Test, Signal-to-Noise Ratio and Normalized Inter-Class Variance testing methods. CONFISCA can on-the-fly switch between its two modes of operation: The High-Performance and High-Security by having only one instance of the cipher. This gives us the flexibility to trade performance/energy with security, based on the actual critical needs.

scholarly journals Tandem Deep Learning Side-Channel Attack on FPGA Implementation of AES

2021 ◽  
Vol 2 (5) ◽  
Author(s):  
Huanyu Wang ◽  
Elena Dubrova
Keyword(s):  
Deep Learning ◽  
Power Analysis ◽  
Fpga Implementation ◽  
Side Channel ◽  
Neural Network Classifier ◽  
Side Channel Attacks ◽  
Learning Techniques ◽  
Cryptographic Algorithms ◽  
Potential Benefits ◽  
Single Neural Network

AbstractSide-channel attacks have become a realistic threat to implementations of cryptographic algorithms, especially with the help of deep-learning techniques. The majority of recently demonstrated deep-learning side-channel attacks use a single neural network classifier to extract the secret from implementations of cryptographic algorithms. The potential benefits of combining multiple classifiers using the ensemble learning method have not been fully explored in the side-channel attack’s context. In this paper, we propose a tandem approach for the attack in which multiple models are trained on different attack points but are used in parallel to recover the key. Such an approach allows us to considerably reduce (33.5% on average) the number of traces required to recover the key from an FPGA implementation of AES by power analysis. We also show that not all combinations of classifiers improve the attack efficiency.

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