Characteristic Analysis of Side Channel Attacks and Various Power Analysis Attack Techniques

2020 ◽  
pp. 182-195
Author(s):  
Shaminder Kaur ◽  
Balwinder Singh ◽  
Harsimran Jit Kaur
Keyword(s):  
Embedded Systems ◽  
Power Analysis ◽  
Side Channel ◽  
Characteristic Analysis ◽  
Side Channel Attacks ◽  
Design Constraints ◽  
Secure Systems ◽  
Cryptographic Algorithms ◽  
Active Attacks ◽  
Insight Into

Embedded systems have a plethora of security solutions and encryption protocols that can protect them against a multitude of attacks. Hardware engineers infuse lot of time and effort in implementing cryptographic algorithms, keeping the analysis of design constraints into rumination. When it comes to designs in potential hostile environment, engineers face a challenge for building resistance-free embedded systems against attacks called side channel attacks. Therefore, there is a strong need to address issues related to side channel attacks. This chapter will provide an insight into the field of hardware security, and will provide a deep investigation of various types of side channel attacks and better understanding of various power analysis tools, which will further give researchers a vision to build efficient and secure systems in order to thwart attacks. This chapter mainly focuses on passive attacks as compared to active attacks since passive attacks are easy to perform and lot of research is going on these attacks.

scholarly journals Tandem Deep Learning Side-Channel Attack on FPGA Implementation of AES

2021 ◽  
Vol 2 (5) ◽  
Author(s):  
Huanyu Wang ◽  
Elena Dubrova
Keyword(s):  
Deep Learning ◽  
Power Analysis ◽  
Fpga Implementation ◽  
Side Channel ◽  
Neural Network Classifier ◽  
Side Channel Attacks ◽  
Learning Techniques ◽  
Cryptographic Algorithms ◽  
Potential Benefits ◽  
Single Neural Network

AbstractSide-channel attacks have become a realistic threat to implementations of cryptographic algorithms, especially with the help of deep-learning techniques. The majority of recently demonstrated deep-learning side-channel attacks use a single neural network classifier to extract the secret from implementations of cryptographic algorithms. The potential benefits of combining multiple classifiers using the ensemble learning method have not been fully explored in the side-channel attack’s context. In this paper, we propose a tandem approach for the attack in which multiple models are trained on different attack points but are used in parallel to recover the key. Such an approach allows us to considerably reduce (33.5% on average) the number of traces required to recover the key from an FPGA implementation of AES by power analysis. We also show that not all combinations of classifiers improve the attack efficiency.

scholarly journals Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 13
Author(s):  
Ivan Bow ◽  
Nahome Bete ◽  
Fareena Saqib ◽  
Wenjie Che ◽  
Chintan Patel ◽  
...  
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Dynamic Partial Reconfiguration ◽  
Channel Power ◽  
Diversity Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Algorithms

This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques.

scholarly journals A Countermeasure against DPA on SIMON with an Area-Efficient Structure

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 240 ◽  
Author(s):  
Yuanyuan Zhang ◽  
Ning Wu ◽  
Fang Zhou ◽  
Jinbao Zhang ◽  
Muhammad Yahya
Keyword(s):  
Circuit Design ◽  
Power Analysis ◽  
Fault Injection ◽  
Low Cost ◽  
T Test ◽  
Side Channel ◽  
Cryptographic Algorithms ◽  
Randomization Scheme ◽  
The Cost ◽  
Area Efficient

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, we review and analyze the architecture of SIMON algorithm. Secondly, we prove the threat of DPA attack to SIMON by launching actual DPA attack on SIMON 32/64 circuit. Thirdly, a low-cost power randomization scheme is proposed by combining fault injection with double rate technology, and the corresponding circuit design is implemented. To the best of our knowledge, this is the first scheme that applies the combination of fault injection and double rate technology to the DPA-resistance. Finally, the t-test is used to evaluate the security mechanism of the proposed designs with leakage quantification. Our experimental results show that the proposed design implements DPA-resistance of SIMON algorithm at certain overhead the cost of 47.7% LUTs utilization and 39.6% registers consumption. As compared to threshold implementation and bool mask, the proposed scheme has greater advantages in resource consumption.

scholarly journals The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1102
Author(s):  
Fang Zhou ◽  
Benjun Zhang ◽  
Ning Wu ◽  
Xiangli Bu
Keyword(s):  
Linear Transformation ◽  
Power Analysis ◽  
Side Channel ◽  
Random Delay ◽  
Side Channel Attacks ◽  
Differential Power Analysis ◽  
Operation Method ◽  
Encryption And Decryption ◽  
Power Curves ◽  
Random Insertion

In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing the glitch data generated by the S-box of SM4 with different inputs, the security against glitch attacks was confirmed. Then, the DPA (Differential Power Analysis) was performed on the designed circuit. The key could not be successfully obtained even in the case of 100,000 power curves, so that the safety of SM4 against DPA is verified. Finally, using Synopsys DC (Design Compiler, Mountain View, CA94043DC, USA) to synthesize the designed circuit, the results show that the area of the designed circuit in the SMIC 0.18 process is 82,734 μm2, which is 48% smaller than results reported in other papers.

Optical Fault Injection Attacks against Cipher Chip

2014 ◽  
Vol 1044-1045 ◽  
pp. 1498-1502 ◽  
Author(s):  
Hong Sheng Wang ◽  
Dao Gang Ji ◽  
Yang Zhang ◽  
Kai Yan Chen ◽  
Kai Song
Keyword(s):  
Fault Injection ◽  
Side Channel ◽  
Side Channel Attack ◽  
Side Channel Attacks ◽  
Secret Information ◽  
Injection Attacks ◽  
Cryptographic Algorithms ◽  
Fault Injection Attacks

Cipher chips, such as microprocessors, are playing the important role in most cryptosystems, and implementing many public cryptographic algorithms. However, Side channel attacks pose serious threats to Cipher chips. Optical Side channel attack is a new kind of method against cipher chips. Two methods are presented in this paper, which shows how to implement optical fault injection attacks against RSA and AES algorithms running on AT89C52 microchip, and demonstrates how to exploit secret information under attack.

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