scholarly journals Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 607
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Single Mode ◽  
Triple Modular Redundancy ◽  
Mode Operation ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Field Programmable ◽  
Modular Redundancy ◽  
Multi Mode

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

scholarly journals Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

2018 ◽  
Vol 9 (1) ◽  
pp. 20 ◽  
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Delay Lines ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Resolution Improvement ◽  
Field Programmable ◽  
Gate Array ◽  
Set Up

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

Bend-loss control of multi-mode fiber power amplifiers producing single-mode operation

2005 ◽  
Author(s):  
Shy Acco ◽  
Yoav Sintov ◽  
Yaakov Glick ◽  
Ori Katz ◽  
Yehuda Nafcha ◽  
...  
Keyword(s):  
Power Amplifiers ◽  
Single Mode ◽  
Single Mode Operation ◽  
Mode Operation ◽  
Loss Control ◽  
Multi Mode

scholarly journals M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 317
Author(s):  
Jurgen Vandendriessche ◽  
Bruno da Silva ◽  
Lancelot Lhoest ◽  
An Braeken ◽  
Abdellah Touhafi
Keyword(s):  
Real Time ◽  
Hard Core ◽  
Wireless Sensor ◽  
Sound Sources ◽  
Real Time System ◽  
Acoustic Images ◽  
Field Programmable ◽  
Industrial Monitoring ◽  
On Chip ◽  
Multi Mode

Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.

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