Triple modular redundancy used in field programmable neural networks

2017 ◽  
Author(s):  
Martin Krcma ◽  
Zdenek Kotasek ◽  
Jakub Lojda
Keyword(s):  
Neural Networks ◽  
Triple Modular Redundancy ◽  
Field Programmable ◽  
Modular Redundancy

scholarly journals Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 607
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Single Mode ◽  
Triple Modular Redundancy ◽  
Mode Operation ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Field Programmable ◽  
Modular Redundancy ◽  
Multi Mode

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

scholarly journals Real-time classification of hand movements as a basis for intuitive control of grasp neuroprostheses

2020 ◽  
Vol 6 (2) ◽  
Author(s):  
Dmitry Amelin ◽  
Ivan Potapov ◽  
Josep Cardona Audí ◽  
Andreas Kogut ◽  
Rüdiger Rupp ◽  
...  
Keyword(s):  
Neural Networks ◽  
Standard Deviation ◽  
Real Time ◽  
Convolutional Neural Networks ◽  
Recurrent Neural Networks ◽  
Healthy Subjects ◽  
Hand Movements ◽  
Cord Injury ◽  
Field Programmable

AbstractThis paper reports on the evaluation of recurrent and convolutional neural networks as real-time grasp phase classifiers for future control of neuroprostheses for people with high spinal cord injury. A field-programmable gate array has been chosen as an implementation platform due to its form factor and ability to perform parallel computations, which are specific for the selected neural networks. Three different phases of two grasp patterns and the additional open hand pattern were predicted by means of surface Electromyography (EMG) signals (i.e. Seven classes in total). Across seven healthy subjects, CNN (Convolutional Neural Networks) and RNN (Recurrent Neural Networks) had a mean accuracy of 85.23% with a standard deviation of 4.77% and 112 µs per prediction and 83.30% with a standard deviation of 4.36% and 40 µs per prediction, respectively.

scholarly journals Study of single event upsets (SEUS) a survey and analysis

2021 ◽  
Author(s):  
Sheldon Mark Foulds
Keyword(s):  
Error Control ◽  
Hamming Code ◽  
Single Event ◽  
Electronic Circuits ◽  
Error Control Coding ◽  
Computing Systems ◽  
Single Event Upsets ◽  
Triple Modular Redundancy ◽  
Radiation Induced ◽  
Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

scholarly journals A Novel Scheme for Fault Tolerant Computing

2021 ◽  
Vol 3 (1) ◽  
pp. 17-23
Author(s):  
Pramode Ranjan Bhattacharjee ◽  
Keyword(s):  
Fault Tolerant ◽  
Present Scheme ◽  
Triple Modular Redundancy ◽  
Test Input ◽  
Digital Network ◽  
Additional Control ◽  
Majority Voter ◽  
Modular Redundancy ◽  
Primary Output

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

Fifty years of Electronic Hardware Implementations of First and Higher Order Neural Networks

2010 ◽  
pp. 269-285 ◽  
Author(s):  
David R. Selviah ◽  
Janti Shawash
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
High Speed ◽  
Higher Order ◽  
Low Latency ◽  
Real Time Control ◽  
Practical Applications ◽  
Field Programmable ◽  
On Chip ◽  
Electronic Hardware

This chapter celebrates 50 years of first and higher order neural network (HONN) implementations in terms of the physical layout and structure of electronic hardware, which offers high speed, low latency, compact, low cost, low power, mass produced systems. Low latency is essential for practical applications in real time control for which software implementations running on CPUs are too slow. The literature review chapter traces the chronological development of electronic neural networks (ENN) discussing selected papers in detail from analog electronic hardware, through probabilistic RAM, generalizing RAM, custom silicon Very Large Scale Integrated (VLSI) circuit, Neuromorphic chips, pulse stream interconnected neurons to Application Specific Integrated circuits (ASICs) and Zero Instruction Set Chips (ZISCs). Reconfigurable Field Programmable Gate Arrays (FPGAs) are given particular attention as the most recent generation incorporate Digital Signal Processing (DSP) units to provide full System on Chip (SoC) capability offering the possibility of real-time, on-line and on-chip learning.

Sign in / Sign up

Export Citation Format

Share Document