scholarly journals A Virtual Device for Simulation-Based Fault Injection

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 1989
Author(s):  
Maria Muñoz-Quijada ◽  
Luis Sanz ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Open Source ◽  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Design And Implementation ◽  
Virtual Device ◽  
Simulation Based ◽  
Internal States ◽  
Field Programmable ◽  
Speed Up ◽  
Real Hardware

This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

scholarly journals Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

2019 ◽  
Vol 9 (1) ◽  
pp. 148
Author(s):  
Sarmad Ismael ◽  
Omar Tareq ◽  
Yahya Taher Qassim
Keyword(s):  
Field Programmable Gate Array ◽  
Complete System ◽  
Line Drawing ◽  
Three Dimensional ◽  
End Point ◽  
Field Programmable ◽  
Speed Up ◽  
The One ◽  
Scan Conversion ◽  
Number Of Segments

<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>

scholarly journals Open-Source FPGA Coprocessor for the Doppler Emulation of Moving Fluids

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1549
Author(s):  
Stefano Ricci
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Open Source ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Synthetic Signal ◽  
Doppler System ◽  
Wide Range ◽  
Field Programmable ◽  
Moving Fluid

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a particular application. This work presents an open-source coprocessor dedicated to the real-time generation of a synthetic signal that mimics the echoes produced by a moving fluid when investigated by ultrasounds. The coprocessor is implemented in a Field Programmable Gate Array (FPGA) device and integrated in an embedded system. The system can replace the complex and inaccurate flow-rigs employed in laboratorial tests of Doppler ultrasound systems and methods. This paper details the coprocessor and its standard interfaces, and shows how it can be integrated in the wider architecture of an embedded system. Experiments showed its capability to emulate a fluid flowing in a pipe when investigated by an echographic Doppler system.

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