scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

scholarly journals High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1075
Author(s):  
Tuy Nguyen Tan ◽  
Tram Thi Bao Nguyen ◽  
Hanho Lee
Keyword(s):  
Great Reduction ◽  
Processing Time ◽  
High Efficiency ◽  
Path Delay ◽  
Hardware Complexity ◽  
Multiple Path ◽  
Novel Approach ◽  
Encryption And Decryption ◽  
Learning With Errors

A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors.

scholarly journals A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA

2018 ◽  
Vol 10 (1) ◽  
pp. 37
Author(s):  
Periyarselvam K ◽  
Saravanakumar G ◽  
Anand M
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
Digital Signal ◽  
Path Delay ◽  
Hardware Complexity ◽  
Large Power ◽  
Fft Processor ◽  
Novel Design ◽  
Multiplexing Systems ◽  
Single Path

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined radix-3 SDF FFT method has been designed. It has less area and large power consumption and delay. In order to overcome these problems, modified carry select adder structure is used to perform the adder operation for reducing the power consumption and delay. Finally, the MCSLA is integrated into radix-3 SDF FFT processor. The hardware complexity and execution time for implementing radix-3 FFT algorithm can be reduced than other FFTs.

Field programmable gate array implementation of variable-bins high efficiency video coding CABAC decoder with path delay optimisation

2019 ◽  
Vol 13 (6) ◽  
pp. 954-963 ◽  
Author(s):  
Wahiba Menasri ◽  
Abdellah Skoudarli ◽  
Aichouche Belhadj ◽  
Mohamed Salah Azzaz
Keyword(s):  
Video Coding ◽  
Field Programmable Gate Array ◽  
High Efficiency ◽  
Path Delay ◽  
High Efficiency Video Coding ◽  
Field Programmable ◽  
Gate Array

scholarly journals Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

2019 ◽  
Vol 9 (1) ◽  
pp. 148
Author(s):  
Sarmad Ismael ◽  
Omar Tareq ◽  
Yahya Taher Qassim
Keyword(s):  
Field Programmable Gate Array ◽  
Complete System ◽  
Line Drawing ◽  
Three Dimensional ◽  
End Point ◽  
Field Programmable ◽  
Speed Up ◽  
The One ◽  
Scan Conversion ◽  
Number Of Segments

<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>

scholarly journals Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

2019 ◽  
Vol 8 (4) ◽  
pp. 10189-10198 ◽  
Keyword(s):  
High Speed ◽  
Complex Multiplication ◽  
Cmos Technology ◽  
Hardware Complexity ◽  
Processing Application ◽  
Point Support ◽  
Multiplication Operation ◽  
Field Programmable ◽  
Cadence Tool ◽  
Area Efficient

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

scholarly journals Enhancing Apple Maturation Recognition Performance Based on Field Programmable Gate Array Implementation

2019 ◽  
Vol 54 (6) ◽  
Author(s):  
Fouad H. Awad ◽  
Mohammed A. Fadhel ◽  
Khattab M. Ali Alheeti ◽  
Omran Al-Shamma ◽  
Laith Alzubaidi
Keyword(s):  
Parallel Processing ◽  
Field Programmable Gate Array ◽  
Recognition Performance ◽  
Recognition System ◽  
Clustering Technique ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Hardware Designs ◽  
Mature Apple

Recently, several techniques have been developed for vegetable and fruit maturing recognition. Adding hardware designs will enhance the recognition performance. Especially, parallel processing designs efficiently speed up the process functions. This paper utilizes a hardware parallel processing design called field programmable gate array for that purpose. In addition, two different methods; namely K-means clustering and color thresholding are used for recognizing the apple maturation. This study aims to design and implement a mature apple recognition system based on field programmable gate array. The results demonstrate that the color thresholding technique is faster, more reliable and more effective than the K-means clustering technique.

scholarly journals DWT Based Image Steganography with Seven Segment Display Pattern as a Key

2019 ◽  
Vol 8 (10S) ◽  
pp. 164-169 ◽  
Keyword(s):  
Field Programmable Gate Array ◽  
Image Steganography ◽  
Data Embedding ◽  
Secret Key ◽  
Novel Approach ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Reconfigurable Device

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.

Field Programmable Gate Array Implementation for Highly Secured Palm Print Authentication

2020 ◽  
Vol 17 (9) ◽  
pp. 4565-4570
Author(s):  
Rajeev Shrivastava ◽  
Mohammad Javeed ◽  
G. Mallesham
Keyword(s):  
Field Programmable Gate Array ◽  
Wide Scope ◽  
After Effects ◽  
Low Level ◽  
High Speeds ◽  
Field Programmable ◽  
Speed Up ◽  
Transport Line ◽  
Palm Print ◽  
New Research

To guarantee individual ID and profoundly secure recognizable proof issues, biometric innovations will give more prominent security while improving precision. This new innovation has been done lately because of exchange misrepresentation, security breaks, individual ID, and so on. The excellence of biometric innovation is that it gives an exceptional code to every individual and can’t be duplicated or manufactured by others. So as to conquer the withdrawal of finger impression frameworks, this paper proposed a palm-based individual distinguishing proof framework, a promising and new research region in biometric recognizable proof frameworks in light of their uniqueness, adaptability and a quicker and wide scope of high speeds. It gives higher security on biometric unique mark frameworks with rich highlights, for example, wrinkles, constant brushes, mainlines, details focuses and single focuses. The fundamental motivation behind the proposed palm unique finger impression framework is to actualize a framework with higher exactness and speed up palm unique finger impression acknowledgment for some clients. Here, in this we presented an exceptionally ensured palm print recognizable proof framework with intrigue extraction territory (ROI) with a morphological procedure utilizing a two-way un-crushed or course vector (UDBW) change to separate low-level palm fingerprints enrolled capacities for its vector work (FV) and afterward after correlation is by estimating the separation between the palm transporters and the capacity of the palm and the capacity of the enlisted transport line and palm control. The after effects of the recreation show that the proposed biometric recognizable proof framework gives more noteworthy precision and solid distinguishing proof speed.

scholarly journals A Virtual Device for Simulation-Based Fault Injection

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 1989
Author(s):  
Maria Muñoz-Quijada ◽  
Luis Sanz ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Open Source ◽  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Design And Implementation ◽  
Virtual Device ◽  
Simulation Based ◽  
Internal States ◽  
Field Programmable ◽  
Speed Up ◽  
Real Hardware

This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware.

scholarly journals FPGA IMPLEMENTATION OF RED ALGORITHM FOR HIGH SPEED PUPIL ISOLATION

2013 ◽  
pp. 192-197
Author(s):  
PRASHANTH M. ULLAGADDI ◽  
K. N. PUSHPALATHA ◽  
ARAVIND KUMAR GAUTAM
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Iris Recognition ◽  
Recognition Algorithm ◽  
Directional Filtering ◽  
Automated Method ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Computationally Intensive

Iris recognition is an automated method of biometric identification that uses mathematical pattern-recognition techniques on video images of the irises of an individual’s eyes, whose complex random patterns are unique and can be seen from some distance. Modern iris recognition algorithms can be computationally intensive, yet are designed for traditional sequential processing elements, such as a personal computer. However, a parallel processing alternative using Field Programmable Gate Array offers an opportunity to speed up iris recognition. Within the means of this project, iris template generation with directional filtering, which is a computationally expensive, yet parallel portion of a modern iris recognition algorithm, is parallelized on an FPGA system. An algorithm that is both accurate and fast in a hardware design that is small and transportable are crucial to the implementation of this tool. As part of an ongoing effort to meet these criteria, this method improves a iris recognition algorithm, namely pupil isolation. A significant speed-up of pupil isolation by implementing this portion of the algorithm on a Field Programmable Gate Array.

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