scholarly journals Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

2019 ◽  
Vol 9 (1) ◽  
pp. 148
Author(s):  
Sarmad Ismael ◽  
Omar Tareq ◽  
Yahya Taher Qassim
Keyword(s):  
Field Programmable Gate Array ◽  
Complete System ◽  
Line Drawing ◽  
Three Dimensional ◽  
End Point ◽  
Field Programmable ◽  
Speed Up ◽  
The One ◽  
Scan Conversion ◽  
Number Of Segments

<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>

scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA)

2019 ◽  
Author(s):  
Robert Carroll ◽  
Carlos Gutierrez ◽  
Leila Choobineh ◽  
Robert Geer
Keyword(s):  
Field Programmable Gate Array ◽  
Thermal Modeling ◽  
Three Dimensional ◽  
Vertical Direction ◽  
Temperature Fields ◽  
Junction Temperature ◽  
3D Integration ◽  
Equivalent Thermal Conductivity ◽  
Field Programmable ◽  
Gate Array

Abstract Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal integrity, and delay. Further, it facilities heterogeneous integration where additional functionalities can be incorporated into the same package as the FPGA, such as sensors, memories, and RF/analog or photonic chips, etc. Traditionally, devices have always been laid out in a planar format. 3D integration is an architecture wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSVs) in the vertical direction. This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field programmable gate array (3D-AFPGA) design based on an extension of preexisting 2D-FPGA tile designs. Since thermal management of 3D-AFPGA is important, numerical simulations performed to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and three-dimensional temperature fields in the 3D-AFPGA are developed and discussed.

scholarly journals Mathematical Model and FPGA Realization of a Multi-Stable Chaotic Dynamical System with a Closed Butterfly-Like Curve of Equilibrium Points

2021 ◽  
Vol 11 (2) ◽  
pp. 788
Author(s):  
Aceng Sambas ◽  
Sundarapandian Vaidyanathan ◽  
Talal Bonny ◽  
Sen Zhang ◽  
Sukono ◽  
...  
Keyword(s):  
Mathematical Model ◽  
Field Programmable Gate Array ◽  
Equilibrium Points ◽  
Three Dimensional ◽  
Intrinsic Properties ◽  
Chaotic Dynamical System ◽  
Chaotic Model ◽  
Field Programmable ◽  
The Mathematical Model ◽  
New System

This paper starts with a review of three-dimensional chaotic dynamical systems equipped with special curves of balance points. We also propose the mathematical model of a new three-dimensional chaotic system equipped with a closed butterfly-like curve of balance points. By performing a bifurcation study of the new system, we analyze intrinsic properties such as chaoticity, multi-stability, and transient chaos. Finally, we carry out a realization of the new multi-stable chaotic model using Field-Programmable Gate Array (FPGA).

scholarly journals Enhancing Apple Maturation Recognition Performance Based on Field Programmable Gate Array Implementation

2019 ◽  
Vol 54 (6) ◽  
Author(s):  
Fouad H. Awad ◽  
Mohammed A. Fadhel ◽  
Khattab M. Ali Alheeti ◽  
Omran Al-Shamma ◽  
Laith Alzubaidi
Keyword(s):  
Parallel Processing ◽  
Field Programmable Gate Array ◽  
Recognition Performance ◽  
Recognition System ◽  
Clustering Technique ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Hardware Designs ◽  
Mature Apple

Recently, several techniques have been developed for vegetable and fruit maturing recognition. Adding hardware designs will enhance the recognition performance. Especially, parallel processing designs efficiently speed up the process functions. This paper utilizes a hardware parallel processing design called field programmable gate array for that purpose. In addition, two different methods; namely K-means clustering and color thresholding are used for recognizing the apple maturation. This study aims to design and implement a mature apple recognition system based on field programmable gate array. The results demonstrate that the color thresholding technique is faster, more reliable and more effective than the K-means clustering technique.

scholarly journals DWT Based Image Steganography with Seven Segment Display Pattern as a Key

2019 ◽  
Vol 8 (10S) ◽  
pp. 164-169 ◽  
Keyword(s):  
Field Programmable Gate Array ◽  
Image Steganography ◽  
Data Embedding ◽  
Secret Key ◽  
Novel Approach ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Reconfigurable Device

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.

Field Programmable Gate Array Implementation for Highly Secured Palm Print Authentication

2020 ◽  
Vol 17 (9) ◽  
pp. 4565-4570
Author(s):  
Rajeev Shrivastava ◽  
Mohammad Javeed ◽  
G. Mallesham
Keyword(s):  
Field Programmable Gate Array ◽  
Wide Scope ◽  
After Effects ◽  
Low Level ◽  
High Speeds ◽  
Field Programmable ◽  
Speed Up ◽  
Transport Line ◽  
Palm Print ◽  
New Research

To guarantee individual ID and profoundly secure recognizable proof issues, biometric innovations will give more prominent security while improving precision. This new innovation has been done lately because of exchange misrepresentation, security breaks, individual ID, and so on. The excellence of biometric innovation is that it gives an exceptional code to every individual and can’t be duplicated or manufactured by others. So as to conquer the withdrawal of finger impression frameworks, this paper proposed a palm-based individual distinguishing proof framework, a promising and new research region in biometric recognizable proof frameworks in light of their uniqueness, adaptability and a quicker and wide scope of high speeds. It gives higher security on biometric unique mark frameworks with rich highlights, for example, wrinkles, constant brushes, mainlines, details focuses and single focuses. The fundamental motivation behind the proposed palm unique finger impression framework is to actualize a framework with higher exactness and speed up palm unique finger impression acknowledgment for some clients. Here, in this we presented an exceptionally ensured palm print recognizable proof framework with intrigue extraction territory (ROI) with a morphological procedure utilizing a two-way un-crushed or course vector (UDBW) change to separate low-level palm fingerprints enrolled capacities for its vector work (FV) and afterward after correlation is by estimating the separation between the palm transporters and the capacity of the palm and the capacity of the enlisted transport line and palm control. The after effects of the recreation show that the proposed biometric recognizable proof framework gives more noteworthy precision and solid distinguishing proof speed.

RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY

2006 ◽  
Vol 06 (04) ◽  
pp. 641-655
Author(s):  
XIAOYING LI ◽  
ENHUA WU
Keyword(s):  
Field Programmable Gate Array ◽  
Motion Parallax ◽  
Three Dimensional ◽  
Texture Mapping ◽  
Memory Space ◽  
Chip Technology ◽  
Mapping System ◽  
Field Programmable ◽  
Gate Array ◽  
Visual Realism

Relief texture mapping is an image-based rendering technique which can successfully support the representation of 3D surface details and view motion parallax. It has the potential to significantly increase visual realism of rendered geometry while keeping system load constant. In this paper, FPGA (Field Programmable Gate Array) chip technology is applied to this three-dimensional image warping method. A relief texture mapping system has been implemented on a reprogrammable and reconfigurable FPGA board. The algorithm is optimized for the specific architecture and the framework is customized for circuit resources, which can be flexibly changed for other structures. In our design, we take advantage of inherent parallelism of the algorithm by concatenating multiple warping engines and well organizing data in memory space. Experimental results show high image quality with improved rendering speed.

scholarly journals A Virtual Device for Simulation-Based Fault Injection

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 1989
Author(s):  
Maria Muñoz-Quijada ◽  
Luis Sanz ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Open Source ◽  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Design And Implementation ◽  
Virtual Device ◽  
Simulation Based ◽  
Internal States ◽  
Field Programmable ◽  
Speed Up ◽  
Real Hardware

This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware.

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