scholarly journals PA-LIRS: An Adaptive Page Replacement Algorithm for NAND Flash Memory

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2172
Author(s):  
Fangjun Wang ◽  
Xianliang Jiang ◽  
Jifu Huang ◽  
Fuguang Chen
Keyword(s):  
Power Consumption ◽  
Flash Memory ◽  
Storage Systems ◽  
High Reliability ◽  
Low Power Consumption ◽  
Nand Flash ◽  
Storage Medium ◽  
Nand Flash Memory ◽  
Replacement Algorithm ◽  
Compact Size

NAND flash memory is increasingly widely used as a storage medium due to its compact size, high reliability, low-power consumption, and high I/O speed. It is important to select a powerful and intelligent page replacement algorithm for NAND flash-based storage systems. However, the features of NAND flash, such as the asymmetric I/O costs and limited erasure lifetime, are not fully taken into account by traditional strategies. In order to address these existing shortcomings, this paper suggests a new page replacement algorithm, called probability-based adjustable algorithm onlow inter-reference recency set (PA-LIRS). PA-LIRS completely exploits the “recency” and “frequency” information simultaneously to make a replacement decision. PA-LIRS gives a greater probability to clean pages and a smaller probability to dirty pages when evict selection happens. In addition, this proposed algorithm dynamically adjusts the parameter based on the workload pattern to further improve the I/O performance of NAND flash memory. Through a series of comparative experiments on various types of synthetic traces, the results show that PA-LIRS outperforms the previous studies in most cases.

A Ferroelectric NAND Flash Memory for Low-power and Highly Reliable Enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V Low-power CPU and SoC

2010 ◽  
Vol 1250 ◽  
Author(s):  
Kousuke Miyaji ◽  
Teruyoshi Hatanaka ◽  
Shuhei Tanakamaru ◽  
Ryoji Yajima ◽  
Shinji Noda ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Current ◽  
Flash Memory ◽  
Charge Pump ◽  
Memory Cell ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Process Step ◽  
Ferroelectric Layer

AbstractThis paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the Vth of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero Vth memory cell scheme is proposed to best optimize the reliability of the Fe-NAND. The Vth shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced. By using Fe-FETs as diodes in the charge pump and optimizing the Vth of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC. During the read/hold, the Vth of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the Vth increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%.

scholarly journals Flash-Aware Page Replacement Algorithm

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Guangxia Xu ◽  
Lingling Ren ◽  
Yanbing Liu
Keyword(s):  
Flash Memory ◽  
Main Memory ◽  
Consumer Electronics ◽  
Storage Device ◽  
Cost Ratio ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Selection Scheme ◽  
Replacement Algorithm ◽  
Memory Resource

Due to the limited main memory resource of consumer electronics equipped with NAND flash memory as storage device, an efficient page replacement algorithm called FAPRA is proposed for NAND flash memory in the light of its inherent characteristics. FAPRA introduces an efficient victim page selection scheme taking into account the benefit-to-cost ratio for evicting each victim page candidate and the combined recency and frequency value, as well as the erase count of the block to which each page belongs. Since the dirty victim page often contains clean data that exist in both the main memory and the NAND flash memory based storage device, FAPRA only writes the dirty data within the victim page back to the NAND flash memory based storage device in order to reduce the redundant write operations. We conduct a series of trace-driven simulations and experimental results show that our proposed FAPRA algorithm outperforms the state-of-the-art algorithms in terms of page hit ratio, the number of write operations, runtime, and the degree of wear leveling.

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