Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network

This paper presents an always-on Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) using an analog convolutional neural network for image classification in mobile applications. To reduce the power consumption as well as the overall processing time, we propose analog convolution circuits for computing convolution, max-pooling, and correlated double sampling operations without operational transconductance amplifiers. In addition, we used the voltage-mode MAX circuit for max pooling in the analog domain. After the analog convolution processing, the image data were reduced by 99.58% and were converted to digital with a 4-bit single-slope analog-to-digital converter. After the conversion, images were classified by the fully connected processor, which is traditionally performed in the digital domain. The measurement results show that we achieved an 89.33% image classification accuracy. The prototype CIS was fabricated in a 0.11 μm 1-poly 4-metal CIS process with a standard 4T-active pixel sensor. The image resolution was 160 × 120, and the total power consumption of the proposed CIS was 1.12 mW with a 3.3 V supply voltage and a maximum frame rate of 120.

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Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽

10.3390/s20133649 ◽

2020 ◽

Vol 20 (13) ◽

pp. 3649

Author(s):

Minhyun Jin ◽

Hyeonseob Noh ◽

Minkyu Song ◽

Soo Youn Kim

Keyword(s):

Power Consumption ◽

Edge Detection ◽

Low Power ◽

High Speed ◽

Cmos Image Sensor ◽

Image Sensor ◽

Frame Rate ◽

Oxide Semiconductor ◽

Total Power ◽

Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

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On-CMOS Image Sensor Processing for Lane Detection

Sensors ◽

10.3390/s21113713 ◽

2021 ◽

Vol 21 (11) ◽

pp. 3713

Author(s):

Soyeon Lee ◽

Bohyeok Jeong ◽

Keunyeol Park ◽

Minkyu Song ◽

Soo Youn Kim

Keyword(s):

Edge Detection ◽

High Speed ◽

Cmos Image Sensor ◽

Image Sensor ◽

Image Resolution ◽

Lane Detection ◽

Frame Rate ◽

Total Power ◽

Detection Accuracy ◽

Total Power Consumption

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

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CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions

Sensors ◽

10.3390/s21217071 ◽

2021 ◽

Vol 21 (21) ◽

pp. 7071

Author(s):

Alejandro Medina-Santiago ◽

Carlos Arturo Hernández-Gracidas ◽

Luis Alberto Morales-Rosales ◽

Ignacio Algredo-Badillo ◽

Monica Amador García ◽

...

Keyword(s):

Neural Network ◽

Learning Algorithm ◽

Building Blocks ◽

Oxide Semiconductor ◽

Digital Data ◽

Total Power ◽

Gradient Descent Method ◽

Objective Functions ◽

Ann Model ◽

Total Power Consumption

The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 μm technology integrated circuit, with a total power consumption of 46.08 mW, using nine neurons and 36 CMOS operational amplifiers (op-amps). We show the results obtained from the application of integrated circuits for ANNs simulated in PSpice applied to the classification of digital data, demonstrating that the optimization method successfully obtains the synaptic weights and bias values generated by the learning algorithm (Steepest-Descent), for the design of the neural architecture.

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A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor

Sensors ◽

10.3390/s21030743 ◽

2021 ◽

Vol 21 (3) ◽

pp. 743

Author(s):

Zunkai Huang ◽

Jinglin Huang ◽

Li Tian ◽

Ning Wang ◽

Yongxin Zhu ◽

...

Keyword(s):

Dynamic Range ◽

Single Photon ◽

Image Sensor ◽

Oxide Semiconductor ◽

Total Power ◽

Cmos Process ◽

Digital Converter ◽

Delay Element ◽

Time To Digital Converter ◽

Total Power Consumption

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

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