scholarly journals Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

2020 ◽  
Vol 9 (6) ◽  
pp. 1116-1122
Keyword(s):  
Fourier Transform ◽  
Power Consumption ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Single Port ◽  
Local Networks ◽  
Parallel Pipelined ◽  
4G Wireless ◽  
Derived Design ◽  
Point Fast Fourier Transform

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4- stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2 .The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

scholarly journals A 2048-point Split-Radix Fast Fourier Transform Computed using Radix-4 Butterfly Units

2019 ◽  
Vol 8 (4) ◽  
pp. 2043-2046
Keyword(s):  
Fourier Transform ◽  
Power Consumption ◽  
Low Power ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Low Power Consumption ◽  
Signal Flow Graph ◽  
Flow Graph ◽  
Dynamic Power ◽  
Fft Algorithms

For the low-power consumption of fast fourier transform, Split-radix fast Fourier transforms are widely used. SRFFT uses less number of mathematical calculations amongst the different FFT algorithms. Split-radix FFT has the same signal flow graph that of conventional radix-2/4 FFT’s. Therefore, the address generation method is same for SRFFT as of radix-2. A low power SRFFT architecture with modified butterfly units is presented over here. Here, it is shown that the, a 2048-point SRFFT is computed using radix-4 butterfly unist. Dynamic power is saved, on compromising the use of extra hardware. Here, the architecture size is increased from radix-2 to 4 and the dynamic power consumption is evaluated.

IMPLEMENTING FAST FOURIER TRANSFORMS ON DISTRIBUTED-MEMORY MULTIPROCESSSORS USING DATA REDISTRIBUTIONS

1994 ◽  
Vol 04 (04) ◽  
pp. 477-488 ◽  
Author(s):  
S.K.S. GUPTA ◽  
C.-H. HUANG ◽  
P. SADAYAPPAN ◽  
R.W. JOHNSON
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Distributed Memory ◽  
Fourier Transforms ◽  
Experimental Performance ◽  
Minimum Number ◽  
Data Redistribution ◽  
Using Data ◽  
Performance Results ◽  
Fft Algorithms

Implementations of various fast Fourier transform (FFT) algorithms are presented for distributed-memory multiprocessors. These algorithms use data redistribution to localize the computation. The goal is to optimize communication cost by using a minimum number of redistribution steps. Both analytical and experimental performance results on the Intel iPSC/860 system are presented.

SNOCRAFT: A Learning-Oriented Shorthand Notation for Creating, Representing, and Analyzing Fast Fourier Transform Algorithms

1980 ◽  
Vol 17 (3) ◽  
pp. 284-284
Author(s):  
Robert J. Meir ◽  
Sathyanarayan S. Rao
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Reduced Form ◽  
Fast Fourier Transform Algorithm ◽  
Signal Flow Graph ◽  
Shorthand Notation ◽  
The Matrix ◽  
Fourier Algorithm ◽  
Fft Analysis

This paper presents a full and well-developed view of the Fast Fourier Transform (FFT). It is intended for the reader who wishes to learn and develop his own fast Fourier algorithm. The approach presented here utilizes the matrix description of fast Fourier transforms. This approach leads to a systematic method for greatly reducing the complexity and the space required by variety of signal flow graph descriptions. This reduced form is called SNOCRAFT. From this representation, it is then shown how one can derive all possible fast Fourier transform algorithms, including the Weinograd Fourier transform algorithm. It is also shown from the SNOCRAFT representation that one can easily compute the number of multiplications and additions required to perform a specified fast Fourier transform algorithm. After an elementary introduction to matrix representation of fast Fourier transform algorithm, the method of generating all possible fast Fourier transform algorithms is presented in detail and is given in three sections. The first section discusses the Generation of SNOCRAFT and the second section illustrates how Operations on SNOCRAFT are made. These operations include inversion and rotation. The last section deals with the FFT Analysis. In this section, examples are provided to illustrate how one counts the number of multiplications and additions involved in performing the transform that one has developed.

scholarly journals Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

2021 ◽  
Vol 16 (2) ◽  
pp. 1-11
Author(s):  
André Sapper ◽  
Guilherme Paim ◽  
Eduardo Antônio César Da Costa ◽  
Sergio Bampi
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Efficiency ◽  
Cordic Algorithm ◽  
Standard Cell ◽  
Clock Gating ◽  
Power Efficient ◽  
Coordinate Rotation ◽  
Hardware Architectures ◽  
Point Fast Fourier Transform

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

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