2-output Spin Wave Programmable Logic Gate

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing \{AND, OR, NAND, NOR\} and \{XOR and XNOR\} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

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Fan-out enabled spin wave majority gate

10.36227/techrxiv.16608361.v1 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Christoph Adelmann ◽

Florin Ciubotaru ◽

Said Hamdioui ◽

...

Keyword(s):

Spin Wave ◽

State Of The Art ◽

Logic Gate ◽

Logic Circuits ◽

Boolean Logic ◽

Function Evaluation ◽

Majority Gate ◽

Logic Function ◽

Micromagnetic Simulations ◽

Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

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Code Generation from UML Model: State of the Art and Practical Implications

Applied Computer Systems ◽

10.2478/acss-2013-0002 ◽

2013 ◽

Vol 14 (1) ◽

pp. 9-18 ◽

Cited By ~ 1

Author(s):

Andrejs Bajovs ◽

Oksana Nikiforova ◽

Janis Sejans

Keyword(s):

Software Development ◽

Code Generation ◽

State Of The Art ◽

Object Oriented ◽

Object Oriented Programming ◽

Software Components ◽

Model State ◽

Methods And Techniques ◽

Practical Implications

Abstract The paper draws attention to the problem of code generation under advanced software development. In their previous publications the authors already discussed several issues associated with the inconsistency between the generated software components and those expected in respect with the rules for object-oriented programming. The current research is an effort to systematize the information about code generation methods and techniques applied in the task of code generation and to try to answer the question of what is the reason for code generation failing to work correctly.

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4-output Programmable Spin Wave Logic Gate

10.36227/techrxiv.16616095.v1 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Christoph Adelmann ◽

Florin Ciubotaru ◽

Said Hamdioui ◽

...

Keyword(s):

Boolean Function ◽

Spin Wave ◽

Logic Gate ◽

Logic Gates ◽

Data Representation ◽

Output Energy ◽

Element Subset ◽

Ultra Low Power ◽

Computing Paradigm ◽

Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

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Fan-out enabled spin wave majority gate

10.36227/techrxiv.16608361 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Christoph Adelmann ◽

Florin Ciubotaru ◽

Said Hamdioui ◽

...

Keyword(s):

Spin Wave ◽

State Of The Art ◽

Logic Gate ◽

Logic Circuits ◽

Boolean Logic ◽

Function Evaluation ◽

Majority Gate ◽

Logic Function ◽

Micromagnetic Simulations ◽

Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

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4-output Programmable Spin Wave Logic Gate

10.36227/techrxiv.16616095 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Christoph Adelmann ◽

Florin Ciubotaru ◽

Said Hamdioui ◽

...

Keyword(s):

Boolean Function ◽

Spin Wave ◽

Logic Gate ◽

Logic Gates ◽

Data Representation ◽

Output Energy ◽

Element Subset ◽

Ultra Low Power ◽

Computing Paradigm ◽

Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

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2-Output Spin Wave Programmable Logic Gate

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi49217.2020.00021 ◽

2020 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Christoph Adelmann ◽

Florin Ciubotaru ◽

Sorin Cotofana ◽

...

Keyword(s):

Spin Wave ◽

Logic Gate ◽

Programmable Logic

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n-bit Data Parallel Spin Wave Logic Gate

10.36227/techrxiv.16608337 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Florin Ciubotaru ◽

Christoph Adelmann ◽

Sorin Cotofana ◽

...

Keyword(s):

Energy Consumption ◽

Parallel Processing ◽

Spin Wave ◽

Potential Benefit ◽

Input Data ◽

Logic Gate ◽

Object Oriented ◽

Data Sets ◽

Majority Gate ◽

Data Parallel

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures.

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n-bit Data Parallel Spin Wave Logic Gate

10.36227/techrxiv.16608337.v1 ◽

2021 ◽

Author(s):

Abdulqader Mahmoud ◽

Frederic Vanderveken ◽

Florin Ciubotaru ◽

Christoph Adelmann ◽

Sorin Cotofana ◽

...

Keyword(s):

Energy Consumption ◽

Parallel Processing ◽

Spin Wave ◽

Potential Benefit ◽

Input Data ◽

Logic Gate ◽

Object Oriented ◽

Data Sets ◽

Majority Gate ◽

Data Parallel

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures.

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A secure and highly efficient first-order masking scheme for AES linear operations

Cybersecurity ◽

10.1186/s42400-021-00082-w ◽

2021 ◽

Vol 4 (1) ◽

Author(s):

Jingdian Ming ◽

Yongbin Zhou ◽

Huizhong Li ◽

Qian Zhang

Keyword(s):

Cost Reduction ◽

Provable Security ◽

State Of The Art ◽

Side Channel ◽

First Order ◽

Highly Efficient ◽

Non Linear ◽

Device Independence ◽

Practical Implications ◽

Provably Secure

AbstractDue to its provable security and remarkable device-independence, masking has been widely accepted as a noteworthy algorithmic-level countermeasure against side-channel attacks. However, relatively high cost of masking severely limits its applicability. Considering the high tackling complexity of non-linear operations, most masked AES implementations focus on the security and cost reduction of masked S-boxes. In this paper, we focus on linear operations, which seems to be underestimated, on the contrary. Specifically, we discover some security flaws and redundant processes in popular first-order masked AES linear operations, and pinpoint the underlying root causes. Then we propose a provably secure and highly efficient masking scheme for AES linear operations. In order to show its practical implications, we replace the linear operations of state-of-the-art first-order AES masking schemes with our proposal, while keeping their original non-linear operations unchanged. We implement four newly combined masking schemes on an Intel Core i7-4790 CPU, and the results show they are roughly 20% faster than those original ones. Then we select one masked implementation named RSMv2 due to its popularity, and investigate its security and efficiency on an AVR ATMega163 processor and four different FPGA devices. The results show that no exploitable first-order side-channel leakages are detected. Moreover, compared with original masked AES implementations, our combined approach is nearly 25% faster on the AVR processor, and at least 70% more efficient on four FPGA devices.

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