scholarly journals 4-output Programmable Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Boolean Function ◽  
Spin Wave ◽  
Logic Gate ◽  
Logic Gates ◽  
Data Representation ◽  
Output Energy ◽  
Element Subset ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

scholarly journals 4-output Programmable Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Boolean Function ◽  
Spin Wave ◽  
Logic Gate ◽  
Logic Gates ◽  
Data Representation ◽  
Output Energy ◽  
Element Subset ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

Logic Devices with Spin Wave Buses - an Approach to Scalable Magneto-Electric Circuitry

2008 ◽  
Vol 1067 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Yina Wu ◽  
Ji-Young Kim ◽  
Augustin Hong ◽  
...  
Keyword(s):  
Spin Wave ◽  
Room Temperature ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Logic Device ◽  
Logic Devices ◽  
Magnetic Circuits ◽  
Micrometer Scale ◽  
Magnetization Signal

ABSTRACTWe analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1μm2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

CHARACTERIZATION, TEST AND LOGIC SYNTHESIS OF NOVEL CONSERVATIVE AND REVERSIBLE LOGIC GATES FOR QCA

2010 ◽  
Vol 09 (03) ◽  
pp. 201-214 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Logic Gates ◽  
Reversible Logic ◽  
Computing Paradigm ◽  
Scale Integration

Quantum dot cellular automaton (QCA) is an emerging technology in the field of nanotechnology. Reversible logic is emerging as a promising computing paradigm with applications in low-power quantum computing and QCA in the field of very large scale integration (VLSI) design. In this paper, we worked on conservative logic gate (CLG) and reversible logic gate (RLG). We examined that RLG and CLG are two classes of logic family intersecting each other. The intersection of RLG and CLG is parity preserving reversible (PPR) or conservative reversible logic gate (CRLG). We proposed in this paper, three algorithms to find different k × k RLG as well as CLG. Here, we demonstrate only the most promising two proposed gates of different categories. We compared the results with that of the previous Fredkin gate. The result shows that logic synthesis using above two gates will be a promising step towards the low-power QCA design era. We have shown a parity preserving approach to design all possible CLG. We also discuss a coupled Majority–minority-Voter (MmV) in a single nanostructure, dual outputs are driven simultaneously. This MmV gate is used for implementing n variables symmetric functions, testing the conservative gates as we explained that parity must be preserved if Majority and Minority output are same as input as well as output of CLG.

scholarly journals 2-output Spin Wave Programmable Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
Boolean Functions ◽  
State Of The Art ◽  
Logic Gate ◽  
Object Oriented ◽  
Programmable Logic ◽  
Area Reduction ◽  
Gate Structure ◽  
Cmos Implementation ◽  
Practical Implications

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing \{AND, OR, NAND, NOR\} and \{XOR and XNOR\} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

scholarly journals 2-output Spin Wave Programmable Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
Boolean Functions ◽  
State Of The Art ◽  
Logic Gate ◽  
Object Oriented ◽  
Programmable Logic ◽  
Area Reduction ◽  
Gate Structure ◽  
Cmos Implementation ◽  
Practical Implications

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing \{AND, OR, NAND, NOR\} and \{XOR and XNOR\} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

scholarly journals Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Design Complexity ◽  
Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm

2018 ◽  
Vol 67 (5) ◽  
pp. 631-645 ◽  
Author(s):  
Yu Bai ◽  
Ronald F. DeMara ◽  
Jia Di ◽  
Mingjie Lin
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Low Power Computing ◽  
Spintronic Logic

Recent advances in molecular logic gate chemosensors based on luminescent metal organic frameworks

2021 ◽  
Author(s):  
Bei Li ◽  
Dongsheng Zhao ◽  
Feng Wang ◽  
Xiaoxian Zhang ◽  
Wenqian Li ◽  
...  
Keyword(s):  
Logic Gate ◽  
Metal Organic Frameworks ◽  
Logic Gates ◽  
Design Strategies ◽  
Molecular Logic Gate ◽  
Future Developments ◽  
Molecular Logic ◽  
Molecular Logic Gates ◽  
Recent Advances ◽  
Metal Organic

This review covers the latest advancements of molecular logic gates based on LMOF. The classification, design strategies, related sensing mechanisms, future developments, and challenges of LMOFs-based logic gates are discussed.

Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications

2019 ◽  
Vol 28 (10) ◽  
pp. 1950171 ◽  
Author(s):  
Vinay Kumar ◽  
Ankit Singh ◽  
Shubham Upadhyay ◽  
Binod Kumar
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Error Tolerance ◽  
Approximate Computing ◽  
Processing Application ◽  
Error Resilient ◽  
Delay Performance ◽  
Prime Concern

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[Formula: see text]18[Formula: see text]J for 16-bit adder and 5.808E[Formula: see text]18[Formula: see text]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

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