scholarly journals FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

2021 ◽  
Vol 16 ◽  
pp. 278-293
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Data Partitioning ◽  
Input Word ◽  
Trade Off ◽  
Filter Length ◽  
Reverse Conversion ◽  
Residue Number

The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

scholarly journals Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

2021 ◽  
Vol 15 ◽  
pp. 700-712
Author(s):  
B. N. Mohan Kumar ◽  
H. G. Rangaraju
Keyword(s):  
Software Defined Radio ◽  
Filter Design ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Input Word ◽  
Trade Off ◽  
Reverse Translation ◽  
Residue Number ◽  
Fir Filter Design

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

scholarly journals New adaptable three-moduli set {2n+k, 2n − 1, 2n−1 − 1} for residue number system-based finite impulse response implementation

2016 ◽  
Vol 13 (11) ◽  
pp. 20160090-20160090 ◽  
Author(s):  
Ming-Hwa Sheu ◽  
Siang-Min Siao ◽  
Yin-Tsung Hwang ◽  
Chi-Chia Sun ◽  
You-Ping Lin
Keyword(s):  
Impulse Response ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Residue Number

scholarly journals Reverse convertor design for the 4-moduli set {2ⁿ -1,2ⁿ, 2ⁿ +1,2²ⁿ+¹ -1} based on the mixed-radix conversion

2011 ◽  
Vol 24 (1) ◽  
pp. 89-103
Author(s):  
Negovan Stamenkovic ◽  
Bojan Jovanovic
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Hardware Architecture ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Mixed Radix Conversion ◽  
Residue Number

The residue number system (RNS) is an integer system capable of supporting high speed concurrent arithmetic. One of the most important consideration when designing RNS system is reverse conversion. The reverse converter for recently proposed for the four-moduli set {2? -1,2?, 2? +1,2??+? -1} is based on new Chinese remainder theorems II (New CRT-II) [6]. This paper presents an alternative architecture derived by Mixed-Radix conversion for this four-moduli set. Due to the using simple multiplicative inverses of the proposed moduli set, it can considerably reduce the complexity of the RNS to binary converter based on the Mixed-Radix conversion. The hardware architecture for the proposed converter is based on the adders and subtractors, without the needed ROM or multipliers.

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