Shannon Entropy Loss in Mixed-Radix Conversions

This paper models a translation for base-2 pseudorandom number generators (PRNGs) to mixed-radix uses such as card shuffling. In particular, we explore a shuffler algorithm that relies on a sequence of uniformly distributed random inputs from a mixed-radix domain to implement a Fisher–Yates shuffle that calls for inputs from a base-2 PRNG. Entropy is lost through this mixed-radix conversion, which is assumed to be surjective mapping from a relatively large domain of size 2J to a set of arbitrary size n. Previous research evaluated the Shannon entropy loss of a similar mapping process, but this previous bound ignored the mixed-radix component of the original formulation, focusing only on a fixed n value. In this paper, we calculate a more precise formula that takes into account a variable target domain radix, n, and further derives a tighter bound on the Shannon entropy loss of the surjective map, while demonstrating monotonicity in a decrease in entropy loss based on increased size J of the source domain 2J. Lastly, this formulation is used to specify the optimal parameters to simulate a card-shuffling algorithm with different test PRNGs, validating a concrete use case with quantifiable deviations from maximal entropy, making it suitable to low-power implementation in a casino.

Effective Error Control Scheme in Real-Time Wireless Sensor Networks

Wireless Sensor Networks (WSNs) subsist on network of huge numbers of hubs that are distributed in unfriendly environments used for habitat monitoring and to observe changes in phenomena. These hubs are susceptible to faults such as energy exhaustion, hardware glitches, communication link errors, malicious attacks, which may lead to errors in message delivery. However, these systems are typically utilized to convey vital information in remote places. Thus, efficient error identification and correction is thereby required in order to maintain the accuracy of the received message. This paper aimed at designing high speed reverse converter for effective error control codes using Redundant Residue Number System in order to enhance the accuracy of messages delivered for real-time WSNs. In order to attain a greater error correction, a reverse converter which was based on Mixed Radix Conversion was designed for the moduli set {2n+1-1, 2n, 2n-1}. In addition to this moduli, an extra redundant moduli set{2n+1+3, 22n - 3} is also designed for higher correctness. For correction and identification of corrupted values in the original data, maximum likelihood was used. The results obtained show that the suggested moduli set offers low energy utilization and consistency of the received message in real time WSNs.

New Algorithm for Reverse Conversion in Residue Number System

Reverse conversion is an important exercise in achieving the properties of Residue Number System (RNS). Current algorithms available for reverse conversion exhibits greater computational overhead in terms of speed and area. In this paper, we have developed a new algorithm for reverse conversion for two-moduli set and three-moduli set that are very simple and with fewer multiplicative inverse operations than there are in the traditional algorithms like the Chinese Remainder Theorem (CRT) and Mixed Radix Conversion (MRC).

Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2ⁿ- 1, 2ⁿ, 2ⁿ + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

High-Performance Computation in Residue Number System Using Floating-Point Arithmetic

Residue number system (RNS) is known for its parallel arithmetic and has been used in recent decades in various important applications, from digital signal processing and deep neural networks to cryptography and high-precision computation. However, comparison, sign identification, overflow detection, and division are still hard to implement in RNS. For such operations, most of the methods proposed in the literature only support small dynamic ranges (up to several tens of bits), so they are only suitable for low-precision applications. We recently proposed a method that supports arbitrary moduli sets with cryptographically sized dynamic ranges, up to several thousands of bits. The practical interest of our method compared to existing methods is that it relies only on very fast standard floating-point operations, so it is suitable for multiple-precision applications and can be efficiently implemented on many general-purpose platforms that support IEEE 754 arithmetic. In this paper, we make further improvements to this method and demonstrate that it can successfully be applied to implement efficient data-parallel primitives operating in the RNS domain, namely finding the maximum element of an array of RNS numbers on graphics processing units. Our experimental results on an NVIDIA RTX 2080 GPU show that for random residues and a 128-moduli set with 2048-bit dynamic range, the proposed implementation reduces the running time by a factor of 39 and the memory consumption by a factor of 13 compared to an implementation based on mixed-radix conversion.

A Division Algorithm in a Redundant Residue Number System Using Fractions

The residue number system (RNS) is widely used for data processing. However, division in the RNS is a rather complicated arithmetic operation, since it requires expensive and complex operators at each iteration, which requires a lot of hardware and time. In this paper, we propose a new modular division algorithm based on the Chinese remainder theorem (CRT) with fractional numbers, which allows using only one shift operation by one digit and subtraction in each iteration of the RNS division. The proposed approach makes it possible to replace such expensive operations as reverse conversion based on CRT, mixed radix conversion, and base extension by subtraction. Besides, we optimized the operation of determining the most significant bit of divider with a single shift operation of the modular divider. The proposed enhancements make the algorithm simpler and faster in comparison with currently known algorithms. The experimental simulation using Kintex-7 showed that the proposed method is up to 7.6 times faster than the CRT-based approach and is up to 10.1 times faster than the mixed radix conversion approach.

A Scaler Design for the RNS Three-Moduli Set {2n+1−1,2n,2n−1} Based on Mixed-Radix Conversion

Adopting the moduli set [Formula: see text] for different DSP applications instead of the traditional moduli set [Formula: see text] has the advantage of excluding modulus [Formula: see text]. A multiply-and-accumulate modulo [Formula: see text] unit is more demanding than a modulo [Formula: see text] unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set [Formula: see text]. The scaling factor is the power-of-two moduli [Formula: see text]. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set [Formula: see text]. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.