scholarly journals Optimal Test Time for System-on-Chip Designs using Fuzzy Logic and Process Algebra

2010 ◽  
Vol 6 (1) ◽  
pp. 12-17
Author(s):  
Rohini
Keyword(s):  
Fuzzy Logic ◽  
Process Algebra ◽  
System On Chip ◽  
Test Time ◽  
Optimal Test ◽  
On Chip

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques

2019 ◽  
Vol 32 (9) ◽  
pp. 5303-5312 ◽  
Author(s):  
Gokul Chandrasekaran ◽  
Sakthivel Periyasamy ◽  
Karthikeyan Panjappagounder Rajamanickam
Keyword(s):  
Artificial Intelligence ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
On Chip

Study on Bus Assignment Algorithm for SOC Test

2015 ◽  
Vol 713-715 ◽  
pp. 1252-1255
Author(s):  
Xiao Min Li ◽  
Shuang Hua Huang
Keyword(s):  
System On Chip ◽  
Test Time ◽  
Main Concern ◽  
Superposition Method ◽  
Compression Process ◽  
Test Access Mechanism ◽  
Soc Test ◽  
Assignment Algorithm ◽  
Temperature Superposition ◽  
On Chip

The main concern is over rising temperature during the testing of complex system-on-chip (SOC), this paper studies SOC wrapper and test access mechanism (TAM), and proposes an improved algorithm of TAM assignment under the constraints of temperature. The algorithm uses temperature superposition method and adds compression process. This algorithm can find the test structure that uses shorter test time.

Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip

2010 ◽  
Vol 663-665 ◽  
pp. 670-673
Author(s):  
Zhong Liang Pan ◽  
Ling Chen
Keyword(s):  
Genetic Algorithm ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Scheduling Problem ◽  
Good Test ◽  
Cellular Genetic Algorithm ◽  
Scheduling Method ◽  
On Chip ◽  
Feasible Solutions

The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

2006 ◽  
Vol 06 (04) ◽  
pp. 511-530 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
HASSAN A. SALAMY
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
System On Chip ◽  
Precedence Constraints ◽  
Test Scheduling ◽  
Optimal Test ◽  
Power Constraints ◽  
Soc Test ◽  
On Chip ◽  
Minimum System

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

Multiple-Constraint Driven System-on-Chip Test Time Optimization

2005 ◽  
Vol 21 (6) ◽  
pp. 599-611 ◽  
Author(s):  
Julien Pouget ◽  
Erik Larsson ◽  
Zebo Peng
Keyword(s):  
System On Chip ◽  
Test Time ◽  
Time Optimization ◽  
Multiple Constraint ◽  
Driven System ◽  
On Chip

scholarly journals Telecontrolling pada Kandang Jangkrik Berbasis IoT (Internet of Things)

2021 ◽  
Vol 11 (4) ◽  
pp. 200-207
Author(s):  
Mohammad Adib ◽  
Lis Diana Mustafa ◽  
Nugroho Suharto
Keyword(s):  
Fuzzy Logic ◽  
Internet Of Things ◽  
Input Data ◽  
System On Chip ◽  
On Chip

Jangkrik adalah jenis serangga yang unik, memiliki suara khas dan aktif pada malam hari, jangkrik banyak dibudidayakan oleh masyarakat karena dapat menjadi penompang perekonomian masyarakat baik untuk pakan binatang piaraan,campuran pakan ternak,bahan tambahan pangan hingga campuran kosmetik. Aspek yang perlu di perhatikan dalam pembudidayaan jangkrik yaitu faktor lingkungan yang mempengaruhi hidup dan pertumbuhan jangkrik sehari-hari adalah dari sumber nutrisi,suhu dan kelembapan.Maka dari itu dibuatlah alat “Telecontrolling Pada Kandang Jangkrik Berbasis IoT (Internet of Things)”Alat ini menggunakan sensor DHT22 dan RTC untuk mengukur suhu dan kelembapan didalam kandang jangkrik dan RTC untuk mendeteksi waktu. Input data sensor akan diolah oleh ESP32 yang merupakan System on Chip dengan Wi-Fi dan Bluetooth, kemudian di deteksi oleh Fuzzy Logic untuk menentukan output pengaktifannya dan kapan ternak jangkrik waktunya panen akan dikirim melalui aplikasi telegram.Hasil perancangan sistem untuk kontrol dan monitoring berhasil diterapkan pada kandang jangkrik dengan berdasarkan suhu, kelembapan dan waktu. Sistem dapat mengirimkan notifikasi output dan respon sesuai dengan kondisi yang telah ditentukan dengan aplikasi telegram dan penyimpanan data pada website. Pengujian akurasi sensor mendapatkan hasil presentasi ketelitian yang cukup akurat, yaitu pada rata-rata presentase akurasi suhu mendapat milai 98% dan pada kelembapan mendapatkan nilai 97%, dan Pengujian hasil presentase akurasi pada sistem dan simulasi fuzzy dengan menggunakan aplikasi telegram dan matlab mendapatkan nilai presentase akurasi 31,66%.

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