Exploiting error resilience of iterative and accumulation based algorithms for hardware efficiency

Approximate computing (AC) represents a paradigm shift from conventional precise processing to inexact computation but still satisfying the system requirement on accuracy. The rapid progress on the development of diverse AC techniques allows us to apply approximate computing to many computation-intensive applications. However, the utilization of AC techniques could bring in new unique security threats to computing systems. This work does a survey on existing circuit-, architecture-, and compiler-level approximate mechanisms/algorithms, with special emphasis on potential security vulnerabilities. Qualitative and quantitative analyses are performed to assess the impact of the new security threats on AC systems. Moreover, this work proposes four unique visionary attack models, which systematically cover the attacks that build covert channels, compensate approximation errors, terminate normal error resilience mechanisms, and propagate additional errors. To thwart those attacks, this work further offers the guideline of countermeasure designs. Several case studies are provided to illustrate the implementation of the suggested countermeasures.

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Concealment Support and Error Resilience for HEVC to Improve Consumer Quality of Experience

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2021.3069464 ◽

2021 ◽

pp. 1-1

Author(s):

Gosala Kulupana ◽

Dumidu S. Talagala ◽

Hemantha Kodikara Arachchi ◽

Mobolaji Akinola ◽

Anil Fernando

Keyword(s):

Quality Of Experience ◽

Error Resilience

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Binary Interactive Error Resilience Beyond

2020 IEEE 61st Annual Symposium on Foundations of Computer Science (FOCS) ◽

10.1109/focs46700.2020.00051 ◽

2020 ◽

Author(s):

Klim Efremenko ◽

Gillat Kol ◽

Raghuvansh R. Saxena

Keyword(s):

Error Resilience

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Reconfigurable Instruction-Set Application-Tuning for DSP

Journal of Circuits System and Computers ◽

10.1142/s0218126603000787 ◽

2003 ◽

Vol 12 (03) ◽

pp. 333-351 ◽

Cited By ~ 5

Author(s):

B. Mesman ◽

Q. Zhao ◽

N. Busa ◽

K. Leijten-Nowak

Keyword(s):

Current System ◽

High Volume ◽

Tool Support ◽

Instruction Set ◽

Instruction Sets ◽

Application Characteristics ◽

On Chip ◽

Application Tuning ◽

Primary Contribution ◽

Hardware Efficiency

In current System-on-Chip (SoC) design, the main engineering trade-off concerns hardware efficiency and design effort. Hardware efficiency traditionally regards cost versus performance (in high-volume electronics), but recently energy consumption emerged as a dominant criterion, even in products without batteries. "The" most effective way to increase HW efficiency is to exploit application characteristics in the HW. The traditional way of looking at HW design tends to consider it a time-consuming and tedious task, however. Given the current lack of HW designers, and the pressure of time-to-market, clearly a desire exists to fine-balance the merits and effort of tuning your HW to your application. This paper discusses methods and tool support for HW application-tuning at different levels of granularity. Furthermore we treat several ways of applying reconfigurable HW to allow both silicon reuse and the ability to tune the HW to the application after fabrication. Our main focus is on a methodology for application-tuning the architecture of DSP datapaths. Our primary contribution is on reusing and generalizing this methodology to application-tuning DSP instruction sets, and providing tool support for efficient compilation for these instruction sets. Furthermore, we propose an architecure for a reconfigurable instruction-decoder, enabling application-tuning of the instruction-set after fabrication.

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A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis

Applied Sciences ◽

10.3390/app9224733 ◽

2019 ◽

Vol 9 (22) ◽

pp. 4733

Author(s):

Cuiping Shao ◽

Huiyun Li ◽

Zheng Wang ◽

Jiayan Fang

Keyword(s):

Image Processing ◽

Principal Component Analysis ◽

Principal Component ◽

Error Resilience ◽

Component Analysis ◽

Cmos Technology ◽

Error Correcting Codes ◽

Memory Storage ◽

Protection Scheme ◽

Bit Flip

Nanoscale CMOS technology has encountered severe reliability issues especially in on-chip memory. Conventional word-level error resilience techniques such as Error Correcting Codes (ECC) suffer from high physical overhead and inability to correct increasingly reported multiple bit flip errors. On the other hands, state-of-the-art applications such as image processing and machine learning loosen the requirement on the levels of data protection, which result in dedicated techniques of approximated fault tolerance. In this work, we introduce a novel error protection scheme for memory, based on feature extraction through Principal Component Analysis and the modular-wise technique to segment the data before PCA. The extracted features can be protected by replacing the fault vector with the averaged confinement vectors. This approach confines the errors with either single or multi-bit flips for generic data blocks, whilst achieving significant savings on execution time and memory usage compared to traditional ECC techniques. Experimental results of image processing demonstrate that the proposed technique results in a reconstructed image with PSNR over 30 dB, while robust against both single bit and multiple bit flip errors, with reduced memory storage to just 22.4% compared to the conventional ECC-based technique.

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