Reconfigurable Instruction-Set Application-Tuning for DSP

2003 ◽  
Vol 12 (03) ◽  
pp. 333-351 ◽  
Author(s):  
B. Mesman ◽  
Q. Zhao ◽  
N. Busa ◽  
K. Leijten-Nowak
Keyword(s):  
Current System ◽  
High Volume ◽  
Tool Support ◽  
Instruction Set ◽  
Instruction Sets ◽  
Application Characteristics ◽  
On Chip ◽  
Application Tuning ◽  
Primary Contribution ◽  
Hardware Efficiency

In current System-on-Chip (SoC) design, the main engineering trade-off concerns hardware efficiency and design effort. Hardware efficiency traditionally regards cost versus performance (in high-volume electronics), but recently energy consumption emerged as a dominant criterion, even in products without batteries. "The" most effective way to increase HW efficiency is to exploit application characteristics in the HW. The traditional way of looking at HW design tends to consider it a time-consuming and tedious task, however. Given the current lack of HW designers, and the pressure of time-to-market, clearly a desire exists to fine-balance the merits and effort of tuning your HW to your application. This paper discusses methods and tool support for HW application-tuning at different levels of granularity. Furthermore we treat several ways of applying reconfigurable HW to allow both silicon reuse and the ability to tune the HW to the application after fabrication. Our main focus is on a methodology for application-tuning the architecture of DSP datapaths. Our primary contribution is on reusing and generalizing this methodology to application-tuning DSP instruction sets, and providing tool support for efficient compilation for these instruction sets. Furthermore, we propose an architecure for a reconfigurable instruction-decoder, enabling application-tuning of the instruction-set after fabrication.

scholarly journals A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1076 ◽  
Author(s):  
Zulqar Nain ◽  
Rashid Ali ◽  
Sheraz Anjum ◽  
Muhammad Khalil Afzal ◽  
Sung Won Kim
Keyword(s):  
Fault Tolerant ◽  
Current System ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Traffic Load ◽  
Delivery Ratio ◽  
Processing Elements ◽  
System On A Chip ◽  
On Chip ◽  
Network On A Chip

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

scholarly journals An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

Symmetry ◽  
2019 ◽  
Vol 11 (7) ◽  
pp. 938
Author(s):  
Syed Rameez Naqvi ◽  
Ali Roman ◽  
Tallha Akram ◽  
Majed M. Alhaisoni ◽  
Muhammad Naeem ◽  
...  
Keyword(s):  
Assembly Language ◽  
Optimization Method ◽  
Instruction Set ◽  
Mathematical Performance ◽  
Optimization Framework ◽  
And Performance ◽  
Reduced Instruction Set Computer ◽  
High Level ◽  
The Given ◽  
Primary Contribution

Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

scholarly journals SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

2008 ◽  
Vol 2008 ◽  
pp. 1-10
Author(s):  
Sami Boukhechem ◽  
El-Bay Bourennane
Keyword(s):  
Open Source ◽  
System On Chip ◽  
Open Architecture ◽  
Multiprocessor System ◽  
Instruction Set ◽  
Levels Of Abstraction ◽  
Transaction Level Modeling ◽  
Synthesis Tool ◽  
Transaction Level ◽  
On Chip

Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

Performance analysis of application-specific instruction-set routers in networks-on-chip

2021 ◽  
Author(s):  
Jens Rettkowski ◽  
Julian Haase ◽  
Sven Primus ◽  
Michael Hübner ◽  
Diana Göhringer
Keyword(s):  
Performance Analysis ◽  
Instruction Set ◽  
Specific Instruction ◽  
Networks On Chip ◽  
On Chip ◽  
Application Specific

KernelGraph: Understanding the kernel in a graph

2018 ◽  
Vol 18 (3) ◽  
pp. 283-296
Author(s):  
Jianjun Shi ◽  
Weixing Ji ◽  
Jingjing Zhang ◽  
Zhiwei Gao ◽  
Yizhuo Wang ◽  
...  
Keyword(s):  
Large Scale ◽  
Effective Means ◽  
Source Code ◽  
High Volume ◽  
Controlled Study ◽  
Tool Support ◽  
Linux Kernel ◽  
High Level ◽  
Key Techniques ◽  
Automated Tool

The Linux kernel has grown to 20 million lines of code, which have been contributed by almost 14,000 programmers. The complexity of the Linux kernel challenges the kernel maintenance and makes comprehending the kernel more difficult for developers learning the kernel. Automated tool support is crucial for comprehending such a large-scale program involving a high volume of code. In this article, we present KernelGraph, which enhances understanding of the Linux kernel by providing a visual representation of kernel internals. KernelGraph resembles online map systems and facilitates kernel code navigation in an intuitive and interactive way. We describe the key techniques used in KernelGraph to process the vast amount of information in the kernel codebase quickly. We also implemented two applications built atop KernelGraph to enhance kernel comprehension. KernelGraph was presented to 30 participants, who were asked several questions about their kernel comprehension in a controlled study. Our experimental results show that, compared with other source code comprehension tools, KernelGraph improves kernel comprehension by enabling people to visually browse the kernel code and by providing an effective means for exploring the kernel structure. The ability to switch seamlessly between high-level views and source code significantly reduces the gap between source code and high-level mental representation. KernelGraph can be easily extended to support visualizations of other large-scale codebases.

scholarly journals A Signature-Based Power Model for MPSoC on FPGA

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Roberta Piscitelli ◽  
Andy D. Pimentel
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Power Estimation ◽  
System Level ◽  
Estimation Methods ◽  
Instruction Set ◽  
Systems On Chip ◽  
Event Signatures ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

scholarly journals Polylactic acid, a sustainable, biocompatible, transparent substrate material for Organ-On-Chip, and Microfluidic applications

2019 ◽  
Author(s):  
Alfredo E. Ongaro ◽  
Davide Di Giuseppe ◽  
Ali Kermanizadeh ◽  
Allende Miguelez Crespo ◽  
Arianna Mencatti ◽  
...  
Keyword(s):  
Animal Models ◽  
Polylactic Acid ◽  
Small Molecule ◽  
Point Of Care ◽  
High Volume ◽  
Substrate Material ◽  
Lab On Chip ◽  
Transparent Substrate ◽  
On Chip ◽  
Microinjection Moulding

AbstractOrgan-on-chips are miniaturised devices aiming at replacing animal models for drug discovery, toxicology and studies of complex biological phenomena. The field of Organ-On-Chip has grown exponentially, and has led to the formation of companies providing commercial Organ-On-Chip devices. Yet, it may be surprising to learn that the majority of these commercial devices are made from Polydimethylsiloxane (PDMS), a silicone elastomer that is widely used in microfluidic prototyping, but which has been proven difficult to use in industrial settings and poses a number of challenges to experimentalists, including leaching of uncured oligomers and uncontrolled adsorption of small compounds. To alleviate these problems, we propose a new substrate for organ-on-chip devices: Polylactic Acid (PLA). PLA is a material derived from renewable resources, and compatible with high volume production technologies, such as microinjection moulding. PLA can be formed into sheets and prototyped into desired devices in the research lab. In this article we uncover the suitability of Polylactic acid as a substrate material for Microfluidic cell culture and Organ-on-a-chip applications. Surface properties, biocompatibility, small molecule adsorption and optical properties of PLA are investigated and compared with PDMS and other reference polymers.SignificanceOrgan-On-Chip (OOC) technology is a powerful and emerging tool that allows the culture of cells constituting an organ and enables scientists, researchers and clinicians to conduct more physiologically relevant experiments without using expensive animal models. Since the emergence of the first OOC devices 10 years ago, the translation from research to market has happened relatively fast. To date, at least 28 companies are proposing body and tissue on-a chip devices. The material of choice in most commercial organ-on-chip platforms is an elastomer, Polydymethyloxane (PDMS), commonly used in microfluidic R&D. PDMS is however subject to poor reproducibility, and absorbs small molecule compounds unless treated. In this study we show that PLA overcomes all the drawbacks related to PDMS: PLA can be prototyped in less than 45 minutes from design to test, is transparent, not autofluorescent, and biocompatible. PLA-based microfluidic platforms have the potential to transform the OOC industry as well as to provide a sustainable alternative for future Lab-On-Chip and point-of-care devices.

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