Sequential Test Set Compaction in LFSR Reseeding

2011 ◽  
pp. 476-493
Author(s):  
Artur Jutman ◽  
Igor Aleksejev ◽  
Jaan Raik
Keyword(s):  
Optimization Technique ◽  
Fault Coverage ◽  
Sequential Test ◽  
Test Sequence ◽  
Great Similarity ◽  
Sequential Designs ◽  
Pseudorandom Sequences ◽  
Test Set ◽  
Embedded Test ◽  
Test Compaction

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. The authors will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated sequences. The authors will make the main focus on one optimization technique that is applicable to reseeding-based test generators and that uses a test compaction methodology. The technique exploits a great similarity in the way the faults are covered by pseudorandom sequences and by patterns generated for sequential designs. Hence, the test compaction methodology previously developed for the latter problem can be successfully reused in embedded testing.

Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test

2019 ◽  
Author(s):  
Manobendra Nath Mondal ◽  
Animesh Basak Chowdhury ◽  
Manjari Pradhan ◽  
Susmita Sur-Kolay ◽  
Bhargab B. Bhattacharya
Keyword(s):  
Fault Coverage ◽  
Test Set ◽  
Structure Preserving ◽  
Circuit Under Test

Application of Sequential Test Set Compaction to LFSR Reseeding

2008 NORCHIP ◽  
2008 ◽  
Author(s):  
Igor Aleksejev ◽  
Artur Jutman ◽  
Jaan Raik ◽  
Raimund Ubar
Keyword(s):  
Sequential Test ◽  
Test Set ◽  
Lfsr Reseeding ◽  
Test Set Compaction

A Simultaneously Testable PLA with High Fault Coverage and Reduced Test Set

1997 ◽  
Vol 43 (1) ◽  
pp. 41-48 ◽  
Author(s):  
Md Abdul Mottalib ◽  
Abusaleh M Jabir
Keyword(s):  
Fault Coverage ◽  
Test Set

scholarly journals Adaptive random testing with total cartesian distance for black box circuit under test

2020 ◽  
Vol 20 (2) ◽  
pp. 720
Author(s):  
Arbab Alamgir ◽  
Abu Khari A’ain ◽  
Norlina Paraman ◽  
Usman Ullah Sheikh
Keyword(s):  
Computational Complexity ◽  
Test Pattern ◽  
Fault Coverage ◽  
Black Box ◽  
Test Sequence ◽  
Random Testing ◽  
Subsequent Test ◽  
Adaptive Random Testing ◽  
Candidate Set ◽  
Circuit Under Test

<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

Automatic Test Sequence Generation for State Transition Testing via Ant Colony Optimization

2010 ◽  
pp. 161-183 ◽  
Author(s):  
Praveen Ranjan Srivastava ◽  
Baby
Keyword(s):  
Ant Colony Optimization ◽  
Software Testing ◽  
State Transition ◽  
Optimization Technique ◽  
Ant Colony ◽  
State Transitions ◽  
Test Sequence ◽  
Software Systems ◽  
Web Based ◽  
Test Suit

Software testing is a key part of software development life cycle. Due to time, cost and other circumstances, exhaustive testing is not feasible, that’s why there is need to automate the testing process. Generation of the automated and effective test suit is a very difficult task in the software testing process. Effective test suite can decrease the overall cost of testing as well as increase the probability of finding defects in software systems. Testing effectiveness can be achieved by the State Transition Testing which is commonly used in, real time, embedded and web-based kind of software system. State transition testing focuses upon the testing of transitions from one state of an object to other states. The tester’s main job is to test all the possible transitions in the system. This chapter proposed an Ant Colony Optimization technique for automated and fully coverage state-transitions in the system. Through proposed algorithm all the transitions are easily traversed at least once in the test-sequence.

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

2014 ◽  
Vol 56 (4) ◽  
Author(s):  
Stephan Eggersglüß ◽  
Rolf Drechsler
Keyword(s):  
Dynamic Test ◽  
Production Test ◽  
Test Set ◽  
Test Compaction ◽  
Test Sets ◽  
Post Production ◽  
Identification Phase ◽  
Compact Test

AbstractEach chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.

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