A High Linearity Folded Gilbert Mixer for 2.4GHz Application

2011 ◽  
Vol 130-134 ◽  
pp. 3267-3271
Author(s):  
Kang Li ◽  
Chao Xian Zhu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chi Liu ◽  
...  
Keyword(s):  
Superposition Method ◽  
Current Steering ◽  
Third Order ◽  
High Linearity ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Simulation Results ◽  
Lc Tank ◽  
Is Design ◽  
Intercept Point

A 2.4GHz high linearity downconversion mixer is designed with MOSFET transconductance linearization technique. Multiple gated transistors (MGTR) (or derivative superposition) method is adopted in the structure to increase IIP3 of the mixer as well as its convertion gain isn’t degraded. In order to improve the performance of the mixer further, a LC tank is used in the LO stage and two current steering PMOS transistors in load stage. The Mixer is design in TSMC 0.35um SiGe BiCMOS technology. Simulation results show that the mixer achieves 2.88dBm input 1dB compress point, 16.18dBm third-order input intercept point (IIP3) and the conversion gain is 12.97dB.

scholarly journals W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

2019 ◽  
Vol 30 ◽  
pp. 01006
Author(s):  
Alexander Kozhemyakin ◽  
Ivan Kravchenko
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Design Flow ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Fundamental Oscillation ◽  
Simulation Results

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

scholarly journals Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range

2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Zhengyu Sun ◽  
Yuepeng Yan
Keyword(s):  
Current Gain ◽  
Variable Gain Amplifier ◽  
Current Steering ◽  
Gain Bandwidth ◽  
Broad Bandwidth ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Bicmos Process ◽  
Steering Current

A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ftBiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm.

scholarly journals Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1058
Author(s):  
Samuel B.S. Lee ◽  
Hang Liu ◽  
Kiat Seng Yeo ◽  
Jer-Ming Chen ◽  
Xiaopeng Yu
Keyword(s):  
Dynamic Range ◽  
Third Order ◽  
Transimpedance Amplifiers ◽  
Variable Gain ◽  
Gain Variation ◽  
Bicmos Technology ◽  
Capacitive Load ◽  
Sige Bicmos ◽  
Amplifier Stage ◽  
On Chip

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

DESIGN CONSIDERATIONS FOR INTEGRATED MODULATOR DRIVERS IN SILICON GERMANIUM TECHNOLOGY

2005 ◽  
Vol 15 (03) ◽  
pp. 477-495 ◽  
Author(s):  
SHANTHI PAVAN ◽  
MAURICE TARSIA ◽  
STEFFEN KUDSZUS ◽  
DAVID PRITZKAU
Keyword(s):  
Power Supply ◽  
Silicon Germanium ◽  
High Speed ◽  
Design Considerations ◽  
Trade Offs ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Present Design ◽  
Simulation Results ◽  
Modulator Driver

We present design considerations for high speed high swing differential modulator drivers in SiGe BiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.

scholarly journals A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 831 ◽  
Author(s):  
Jingyu Han ◽  
Yu Jiang ◽  
Guiliang Guo ◽  
Xu Cheng
Keyword(s):  
Power Consumption ◽  
Gain Control ◽  
Open Loop ◽  
Low Noise ◽  
Pass Filter ◽  
Filter Order ◽  
High Linearity ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Analog Baseband

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

Sign in / Sign up

Export Citation Format

Share Document