Photovoltaic Evaporative Chimney I–V Measurement System

The photovoltaic evaporative chimney is a novel solar-cooling system that serves a double purpose: it increases the efficiency of the photovoltaic (PV) panels and it cools down a water stream which can be used to dissipate the heat from a refrigeration cycle. One of the major issues arising from the operation of the chimney is the temperature stratification in the panel due to the movement of the air in the chimney. This effect can trigger the activation of the bypass diodes of the module, creating local maximum power points (MPP) that can compromise the grid-tied inverter tracking. To fill this gap, this paper deals with the design and implementation of an I–V curve measurement system to be used in the performance analysis of the system. The I–V curve tracer consists of a capacitive load controlled by a single board computer. The final design includes protections, capacitor charging/discharging power electronics, remote commands inputs, and current, voltage, irradiance, and temperature sensors.The results show that the modules bypass diodes are not activated during the tests, and no local MPPs appear. Moreover, the curves measured show the benefits of the photovoltaic chimney: the cooling effect increases the power generated by the PV panels by around 10%.

A 4 GHz Single-to-Differential Cross-Coupled Variable-Gain Transimpedance Amplifier for Optical Communication

This letter presents an inductorless transimpedance amplifier (TIA) for visible light communication, using the UMC 40 nm CMOS process. It consists of a single-to-differential input stage with a modified cross-coupled regulated cascode design, followed by a modified fT-doubler mid-stage with a combined active inductor and capacitive degeneration design for bandwidth-enhancement and differential output. The mid-stage also has an attached common-mode feedback (CMFB) circuit. Both the input and mid-stages have gain-varying and peaking-varying functions. It has a measured gain range of 37.5–58.7 dBΩ and 4.15 GHz bandwidth using a 0.5 pF capacitive load. The gain range results in an input dynamic range of 33.2 µA–1.46 mA. Its input referred noise current is 10.7 pA/Hz, core DC power consumption is 7.84 mW from a VDDTIA of 1.6 V and core area is 39 µm × 26 µm.

Design of high speed 2-stage OTA for high capacitive load of 120pF and 2.96V

High speed operational transconductance amplifier (OTA) is used to drive high capacitive loads to reduce the charging time while providing adequate gain and stability. A 2-stage amplifier is proposed to provide high slew rate and sufficient gain and stability. 45nm process technology is used to compare performance with differential and telescopic amplifier designs. Resistive feedback and noise-gain compensation techniques are used to drive 120pF load and provide 2.96V at output for a high slew rate of 2.2V/µs.

The Helical Resonator: A Scheme for Radio Frequency Plasma Generation

The helical resonator is a scheme for the production of high voltage at radio frequency, useful for gas breakdown and plasma sustainment, which, through a proper design, enables avoiding the use of a matching network. In this work, we consider the treatment of the helical resonator, including a grounded shield, as a transmission line with a shorted end and an open one, the latter possibly connected to a capacitive load. The input voltage is applied to a tap point located near the shorted end. After deriving an expression for the velocity factor of the perturbations propagating along the line, and in the special case of the shield at infinity also of the characteristic impedance, we calculate the input impedance and the voltage amplification factor of the resonator as a function of the wave number. Focusing on the resonance condition, which maximizes the voltage amplification, we then discuss the effect of the tap point position, dissipation and the optional capacitive load, in terms of resonator performance and matching to the power supply.

A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

Capacitive Load-Based Smart OTF for High Power Rated SPV Module

Solar energy is the most promising renewable resource with an unbounded energy source, capable of meeting all human energy requirements. Solar Photovoltaic (SPV) is an effective approach to convert sunlight into electricity, and it has a promising future with consistently rising energy demand. In this work, we propose a smart solution of outdoor performance characterization of the SPV module utilizing a robust, lightweight, portable, and economical Outdoor Test Facility (OTF) with the Internet of Things (IoT) capability. This approach is focused on the capacitive load-based method, which offers improved accuracy and cost-effective data logging using Raspberry Pi and enables the OTF to sweep during the characterization of the SPV module automatically. A demonstration using an experimental setup is also provided in the paper to validate the proposed OTF. This paper further discusses the advantages of using the capacitive load approach over the resistive load approach. IoT’s inherent benefits empower the proposed OTF method on the backgrounds of real-time tracking, data acquisition, and analysis for outdoor output performance characterization by capturing Current–Voltage (I–V) and Power–Voltage (P–V) curves of the SPV module.