Estimation and Management of Performance Limiting Factors in the Development of 1 kW Peak Power Pulsed Fiber MOPA at 1550 nm

An all-fiber three-stage master oscillator power amplifier (MOPA), based on Erbium and Erbium-Ytterbium co-doped fibers, has been designed and developed. The performance of such a laser is primarily limited by amplified spontaneous emission (ASE), Yb bottlenecking, and non-linear effects. Other important factors, that need to be considered towards performance improvement, are fiber bend diameter and heat generated in the fiber. This paper describes the methodology for the estimation and management of these limiting factors for each amplifier stage. The work presented here is limited to the fibers which are commercially easily available, unlike customised Yb- free large mode area (LMA) Erbium-doped fibers, where very high peak and average powers are being reported due to the absence of Yb ASE. Presented experimental results and discussion shall be beneficial for the fiber laser amplifier designers. With suitable management, 1 kW peak power pulses of 30 ns duration at 200 kHz repetition rate have been achieved with 30 % optical efficiency. The collimated output of 6 W average power (limited by Yb ASE) with high beam quality (M2 ≈ 1.6) at 1550 nm can be employed for a variety of applications. By adding additional amplifier stages, power can be scaled further.

Monolithic Integrated High Frequency GaN DC-DC Buck Converters with High Power Density Controlled by Current Mode Logic Level Signal

Integration is a key way to improve the switching frequency and power density for a DC-DC converter. A monolithic integrated GaN based DC-DC buck converter is realized by using a gate driver and a half-bridge power stage. The gate driver is composed of three stages (amplitude amplifier stage, level shifting stage and resistive-load amplifier stage) to amplify and modulate the driver control signal, i.e., CML (current mode logic) level of which the swing is from 1.1 to 1.8 V meaning that there is no need for an additional buffer or preamplifier for the control signal. The gate driver can provide sufficient driving capability for the power stage and improve the power density efficiently. The proposed GaN based DC-DC buck converter is implemented in the 0.25 μm depletion mode GaN-on-SiC process with a chip area of 1.7 mm × 1.3 mm, which is capable of operating at high switching frequency up to 200 MHz and possesses high power density up to 1 W/mm2 at 15 V output voltage. To the authors’ knowledge, this is the highest power density for GaN based DC-DC converter at the hundreds of megahertz range.

Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

ANALYSIS OF THE CONDITIONS OF OCCURRENCE AND SUPPRESSION OF LATERAL VIBRATIONS IN MICROWAVE POWER FETS

Lateral instability is inherent in power transistors structures, consisting of several simple transistors connected in parallel. The large number of transistor elements complicates the analysis of such instability. The introduction of suppressing resistors makes it possible to prevent the occurrence of lateral oscillations, however there are no unambiguous criteria for achieving stability this way. The matter is further complicated by the fact that transistor exhibits nonlinear operation in a typical amplifier stage, and the operating conditions in many cases correspond to a relatively wide range of frequencies. In this paper, we present an analysis of lateral instability of a power amplifier stage, created on a basis of modern GaN field-effect transistor (FET). We had designed all dies and circuits for this FET. The main feature of the analysis is that we carried it out in the time domain, which made possible to estimate the stability of the stage not only under the excitation power pulse, but also after the end of the pulse. Our approach makes it possible to assess the stability of the amplifier between the excitation pulses, which is very important from the operational point of view. We calculated the estimates of operational stability and stability factor using a simplified transistor model, with the multi-element model reduced to a two-element model. Nevertheless, the results of the estimates retain their significance in real conditions, when the introduction of suppressing resistors creates a significant margin of stability, including the actual operating frequency band of the stage. To date, the data we have obtained after the manufacture of the samples only partially confirms the calculated estimates, due to the complexity of managing the experimental studies. However, there are no recorded results, which deny our estimates for the model.

A Low Input Referred Noise Dynamic Comparator for High Speed Applications

Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz

Design of High Stability Factor Lna using Cascade Mosfet at 850MHz Rf Frequency

Controlling noise is the primary effort in any amplifier. LNA (Low Noise Amplifier) will control the noise in front panel of amplifier stage as per FRISS law. Instead of single MOS in LNA , cascaded the MOS generates the stability factor in a better way in 850MHz RF frequency at load impedance of 50Ω. But additionally capacitor inserted cascaded MOS will pull down the stability factor. Cascasded MOS LNA have a stability factor of 1.387 and Noise Figure(dB) of 0.518

Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.