scholarly journals W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

2019 ◽  
Vol 30 ◽  
pp. 01006
Author(s):  
Alexander Kozhemyakin ◽  
Ivan Kravchenko

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

2019 ◽  
Vol 30 ◽  
pp. 01004
Author(s):  
Vadim Budnyaev ◽  
Valeriy Vertegel

This paper presents the simulation results of the W-band 3-stage low noise amplifier which is designed in 0.13 μm SiGe BiCMOS technology. The LNA achieves a peak S21 of 24.1 dB and noise figure of 6 dB at 80 GHz with 3 dB bandwidth of 14 GHz from 73 to 87 GHz. S11 is better than 11 dB. The simulated input 1 dB compression point is –23 dBm at 80 GHz with low power consumption of 26 mW from 1.2 V voltage supply. Layout area is 0.36 mm2.


2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.


2011 ◽  
Vol 130-134 ◽  
pp. 3267-3271
Author(s):  
Kang Li ◽  
Chao Xian Zhu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chi Liu ◽  
...  

A 2.4GHz high linearity downconversion mixer is designed with MOSFET transconductance linearization technique. Multiple gated transistors (MGTR) (or derivative superposition) method is adopted in the structure to increase IIP3 of the mixer as well as its convertion gain isn’t degraded. In order to improve the performance of the mixer further, a LC tank is used in the LO stage and two current steering PMOS transistors in load stage. The Mixer is design in TSMC 0.35um SiGe BiCMOS technology. Simulation results show that the mixer achieves 2.88dBm input 1dB compress point, 16.18dBm third-order input intercept point (IIP3) and the conversion gain is 12.97dB.


2017 ◽  
Vol 9 (6) ◽  
pp. 1231-1239
Author(s):  
Faisal Ahmed ◽  
Muhammad Furqan ◽  
Klaus Aufinger ◽  
Andreas Stelzer

This paper presents the design and measurement results of a high-gain D-band broadband power amplifier (PA) implemented in a 130 nm SiGe BiCMOS technology. The topology of the PA is based on four differential cascode stages with interstage matching networks. A detailed analysis of the frequency behavior of the transimpedance-gain of the common-base stage of the cascode is presented by means of small-signal equivalent circuits, when the proposed four-reactance wideband matching network is used for output matching to the subsequent stage. The effect of the size of the active devices, in achieving a desired gain, bandwidth, and output power, is investigated. The fabricated D-band amplifier is characterized on-wafer demonstrating a peak differential gain and output power of about 25 dB and 11 dBm, respectively, while utilizing a DC power of 262 mW from a 2.7 V supply. The 3-dB small-signal bandwidth of the PA spans from 100 to 180 GHz (limited by the measurement setup), making it the first SiGe-based PA to cover the entire D-band frequency range. The PA achieves a state-of-the-art differential gain-bandwidth product of around 1.4 THz and the highest GBW/PDCratio of 5.2 GHz/mW among all D-Band Si-based PAs.


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