scholarly journals Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1058
Author(s):  
Samuel B.S. Lee ◽  
Hang Liu ◽  
Kiat Seng Yeo ◽  
Jer-Ming Chen ◽  
Xiaopeng Yu
Keyword(s):  
Dynamic Range ◽  
Third Order ◽  
Transimpedance Amplifiers ◽  
Variable Gain ◽  
Gain Variation ◽  
Bicmos Technology ◽  
Capacitive Load ◽  
Sige Bicmos ◽  
Amplifier Stage ◽  
On Chip

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Dynamic Range ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Control Range ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Commercial Technology ◽  
Sige Bicmos ◽  
Analysis Design

Abstract Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured.

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

scholarly journals 10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Communication Systems ◽  
Power Efficiency ◽  
High Speed ◽  
Closed Loop ◽  
Dynamic Range ◽  
Data Converters ◽  
Fully Differential ◽  
Biquad Filter ◽  
Bicmos Technology ◽  
Sige Bicmos

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

scholarly journals Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range

2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Zhengyu Sun ◽  
Yuepeng Yan
Keyword(s):  
Current Gain ◽  
Variable Gain Amplifier ◽  
Current Steering ◽  
Gain Bandwidth ◽  
Broad Bandwidth ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Bicmos Process ◽  
Steering Current

A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ftBiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm.

80-GHz-band low-power sub-harmonic mixer IC with a bottom-LO-configuration in 130-nm SiGe BiCMOS

2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Conversion Gain ◽  
Power Requirement ◽  
Harmonic Mixer ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip ◽  
Marchand Balun

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

A High Linearity Folded Gilbert Mixer for 2.4GHz Application

2011 ◽  
Vol 130-134 ◽  
pp. 3267-3271
Author(s):  
Kang Li ◽  
Chao Xian Zhu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chi Liu ◽  
...  
Keyword(s):  
Superposition Method ◽  
Current Steering ◽  
Third Order ◽  
High Linearity ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Simulation Results ◽  
Lc Tank ◽  
Is Design ◽  
Intercept Point

A 2.4GHz high linearity downconversion mixer is designed with MOSFET transconductance linearization technique. Multiple gated transistors (MGTR) (or derivative superposition) method is adopted in the structure to increase IIP3 of the mixer as well as its convertion gain isn’t degraded. In order to improve the performance of the mixer further, a LC tank is used in the LO stage and two current steering PMOS transistors in load stage. The Mixer is design in TSMC 0.35um SiGe BiCMOS technology. Simulation results show that the mixer achieves 2.88dBm input 1dB compress point, 16.18dBm third-order input intercept point (IIP3) and the conversion gain is 12.97dB.

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