scholarly journals Application of New Matching Technique in Doherty Amplifier

2013 ◽  
Vol 278-280 ◽  
pp. 1091-1094
Author(s):  
Jun Chen ◽  
Guo Qing Shen ◽  
Kai Xiong Su
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Computer Software ◽  
High Linearity ◽  
Matching Technique ◽  
Power Operation ◽  
Doherty Power Amplifier ◽  
Doherty Amplifier

According to the shortage of the traditional offset line in Doherty power amplifier, a new offset line technique is proposed to match carrier amplifier with the load and to improve the performance of the Doherty amplifier. By simulation of the computer software, a higher efficiency is obtained using the new offset line comparing the two kinds of offset lines. The new offset line matching technique could be applied in the system with high linearity and low power operation.

scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

A planner Doherty power amplifier with harmonic suppression with open and short ended stubs

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Saeedeh Lotfi ◽  
Saeed Roshani ◽  
Sobhan Roshani ◽  
Maryam Shirzadian Gilan
Keyword(s):  
Power Amplifier ◽  
Power Divider ◽  
Harmonic Suppression ◽  
Power Added Efficiency ◽  
Main Amplifier ◽  
Inverse Topology ◽  
Doherty Power Amplifier ◽  
Amplifier Design ◽  
Doherty Amplifier ◽  
Class F

Abstract This paper presents a new Doherty power amplifier (DPA) with harmonics suppression. A Wilkinson power divider (WPD) with open-ended and short-ended stubs is designed to suppress unwanted signals. To design the power divider in the circuit of the DPA, even and odd mode analyses are utilized. The proposed design operates at range of 1.2–1.6 GHz. The linearity of the suggested DPA is increased about 6 dBm, in comparison with the main amplifier. The designed Doherty amplifier has a power added efficiency (PAE), drain efficiency (DE) and Gain about 60, 61% and 19 dB, respectively. The designed WPD suppresses 2nd up to 14th harmonics with more than 20 dB suppression level, which is useful for suppressing unwanted harmonics in DPA design. ATF-34143 transistors (pHEMT technology) are used for this DPA amplifier design. The main amplifier has class-F topology and class-F inverse topology is used for auxiliary amplifier.

scholarly journals A Review of Efficiency Improvement Techniques in Modern Communication Systems

2021 ◽  
Vol 23 (07) ◽  
pp. 656-658
Author(s):  
Peddi Saurabh ◽  
◽  
Poornima Asuti ◽  
Prof. Deepika P ◽  
◽  
...  
Keyword(s):  
Power Amplifier ◽  
Communication Systems ◽  
Research Trends ◽  
Efficiency Improvement ◽  
Operational Principle ◽  
Doherty Power Amplifier ◽  
Doherty Amplifier

This paper discusses Doherty Power Amplifier(DPA) and its evolution over the years. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. The different research trends, all aimed to improve the advantages of the Doherty scheme and to solve its inherent drawbacks, are discussed.

A High Linearity and Efficiency Doherty Power Amplifier for Retrodirective Communication

PIERS Online ◽  
2008 ◽  
Vol 4 (2) ◽  
pp. 151-156 ◽  
Author(s):  
Xiaoqun Chen ◽  
Yuchun Guo ◽  
Xiaowei Shi
Keyword(s):  
Power Amplifier ◽  
High Linearity ◽  
Doherty Power Amplifier

scholarly journals A Doherty Power Amplifier with Large Back-Off Power Range Using Integrated Enhancing Reactance

2018 ◽  
Vol 2018 ◽  
pp. 1-8
Author(s):  
Wa Kong ◽  
Jing Xia ◽  
Fan Meng ◽  
Chao Yu ◽  
Lixia Yang ◽  
...  
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Impedance Matching ◽  
Dual Band ◽  
Matching Networks ◽  
Measurement Results ◽  
Linearity Improvement ◽  
Saturated Output Power ◽  
Doherty Power Amplifier ◽  
Power Region

A symmetric Doherty power amplifier (DPA) based on integrated enhancing reactance (IER) was proposed for large back-off applications. The IER was generated using the peaking amplifier with the help of a desired impedance transformation in the low-power region to enhance the back-off efficiency of the carrier amplifier. To convert the impedances properly, both in the low-power region and at saturation, a two-impedance matching method was employed to design the output matching networks. For verification, a symmetric DPA with large back-off power range over 2.2–2.5 GHz was designed and fabricated. Measurement results show that the designed DPA has the 9 dB back-off efficiency of higher than 45%, while the saturated output power is higher than 44 dBm over the whole operation bandwidth. When driven by a 20 MHz LTE signal, the DPA can achieve good average efficiency of around 50% with adjacent channel leakage ratio of about –50 dBc after linearization over the frequency band of interest. The linearity improvement of the DPA for multistandard wireless communication system was also verified with a dual-band modulated signal.

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