scholarly journals Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
The Novel ◽  
Ultra Low Power ◽  
Design And Optimization ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier ◽  
Insertion Losses

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

scholarly journals A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

2021 ◽  
Author(s):  
Pouya Jahanian ◽  
Azadeh Norouzi Kangarshahi
Keyword(s):  
Power Amplifier ◽  
Transmission Lines ◽  
Average Power ◽  
Wide Band ◽  
High Gain ◽  
Input Power ◽  
Power Ratio ◽  
Class Ab ◽  
Power Added Efficiency ◽  
Doherty Power Amplifier

Abstract In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.

scholarly journals LOW POWER SI-BASED POWER AMPLIFIER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (9) ◽  
pp. 307 ◽  
Author(s):  
Wei Cai ◽  
Cheng Li ◽  
Heng Gu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Amplifier ◽  
Process Variations ◽  
Cmos Technology ◽  
Total Power ◽  
Power Added Efficiency ◽  
Trade Offs ◽  
Total Power Consumption ◽  
Class B

<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>

scholarly journals 12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers

2016 ◽  
Vol 11 (2) ◽  
pp. 97-105
Author(s):  
Bernardo Leite ◽  
Eric Kerhervé ◽  
Didier Belot
Keyword(s):  
Power Amplifier ◽  
Rejection Rate ◽  
Cmos Technology ◽  
Common Source ◽  
Output Stage ◽  
Power Added Efficiency ◽  
Matching Networks ◽  
Insertion Losses ◽  
Better Than ◽  
28 Nm

This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Sign in / Sign up

Export Citation Format

Share Document