A Novel Quasi-Cyclic LDPC Codes Construction Method for High-Speed Parallel Decoding

2013 ◽  
Vol 347-350 ◽  
pp. 3702-3707
Author(s):  
Ming Ke Dong ◽  
Da Wang ◽  
Ya Dan Zheng ◽  
Shang Zhu Wu ◽  
Hai Ge Xiang
Keyword(s):  
High Speed ◽  
Block Size ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Data Access ◽  
Construction Method ◽  
Parity Check ◽  
Code Construction ◽  
Low Density Parity Check ◽  
Efficient Decoding

The decoding parallelism of quasi-cyclic low density parity check (QC-LDPC) codes, an important realization factor of LDPC codes, is limited by the block size. Joint row-column (JRC) decoding algorithm, an efficient decoding technique having low computation cost and small iteration number, also suffers from the decoding parallelism limitation in QC-LDPC application. In this paper, a novel LDPC-code construction method is presented and validated. This method constructs the row sets to eliminate the data access conflicts, and it clearly enhances the decoding parallelism while avoids any degradation of bit error rate (BER) performance.

An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel

2013 ◽  
Vol 347-350 ◽  
pp. 1864-1867
Author(s):  
Ning Hao ◽  
Yang An Zhang ◽  
Jin Nan Zhang ◽  
Ming Lun Zhang ◽  
Xue Guang Yuan
Keyword(s):  
High Speed ◽  
System Simulation ◽  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Coherent Light ◽  
Line System ◽  
Low Density Parity Check ◽  
Atmospheric Channel ◽  
Ber Performance

Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

scholarly journals Constructing High-Rate QC-LDPC Codes with Large-Girth based on Shortened Array Codes

2011 ◽  
Vol 1 (03) ◽  
Author(s):  
Xu Chen ◽  
Francis C. M. Lau
Keyword(s):  
Ldpc Codes ◽  
High Rate ◽  
Minimum Length ◽  
Low Density ◽  
Parity Check ◽  
Error Performance ◽  
Code Construction ◽  
Array Codes ◽  
Low Density Parity Check ◽  
Large Girth

In this paper, we aim at constructing high-rate quasi-cyclic low-density parity-check (QC-LDPC) codes with girth-10 based on shortened array codes. Our first contribution is the derivation of analytic results on the maximum number of columns for shortened array codes of different girths. Then, inspired by the analysis, we propose a code construction method for column-weight-three codes. We further compare the minimum length and the error performance of the column-weight-three codes constructed by the proposed algorithm and those found by the conventional greedy construction algorithm. We show that the proposed method is more effective than the conventional greedy algorithm in the sense that the minimum length of the codes constructed using the proposed method to achieve different code rates is comparative or much shorter than those constructed using the greedy construction.

Study on Ameliorating the SCG-LDPC Code for High-Speed Optical Communication Systems

2012 ◽  
Vol 571 ◽  
pp. 224-228
Author(s):  
Jian Guo Yuan ◽  
Qing Zhen Tong ◽  
Liang Xu
Keyword(s):  
Optical Communication ◽  
Communication Systems ◽  
High Speed ◽  
Simulation Analysis ◽  
Ldpc Code ◽  
Construction Method ◽  
Parity Check ◽  
Computation Complexity ◽  
Optical Communication Systems ◽  
Hardware Realization

A novel ameliorated construction method of low density parity check(LDPC) codes, based on the construction method of Systematically Constructed Gallager(SCG) (4,k) code, is proposed. This method, compared with the construction method of SCG(4,k) code ameliorated before, has some advantages such as saving storage space and reducing computation complexity in the hardware realization. And a novel SCG-LDPC(3969,3720) code with the same 93.7% code-rate as classic RS(255,239) code and LDPC(32640,30592) code in ITU-T G.975.1 recommendation is constructed by the proposed method. The simulation analysis results show that this novel SCG-LDPC(3969,3720) code has better error-correction performance and lower decoding complexity than those of a classic RS(255,239) code and LDPC(32640,30592) code. Therefore, the SCG-LDPC(3969,3720) code can be better suitable for high-speed optical communication systems.

scholarly journals On Analyzing LDPC Codes over Multiantenna MC-CDMA System

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
S. Suresh Kumar ◽  
M. Rajaram
Keyword(s):  
Communication Systems ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Cdma System ◽  
Low Density ◽  
Parity Check ◽  
Simple Method ◽  
Broadband Wireless ◽  
Low Density Parity Check ◽  
Code Division Multiple

Multiantenna multicarrier code-division multiple access (MC-CDMA) technique has been attracting much attention for designing future broadband wireless systems. In addition, low-density parity-check (LDPC) code, a promising near-optimal error correction code, is also being widely considered in next generation communication systems. In this paper, we propose a simple method to construct a regular quasicyclic low-density parity-check (QC-LDPC) code to improve the transmission performance over the precoded MC-CDMA system with limited feedback. Simulation results show that the coding gain of the proposed QC-LDPC codes is larger than that of the Reed-Solomon codes, and the performance of the multiantenna MC-CDMA system can be greatly improved by these QC-LDPC codes when the data rate is high.

scholarly journals High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

2021 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Ldpc Codes ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Chip Area ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
The One

<p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.</p>

scholarly journals An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

2021 ◽  
Vol 11 (6) ◽  
pp. 4774
Author(s):  
Mouhcine Razi ◽  
Mhammed Benhayoun ◽  
Anass Mansouri ◽  
Ali Ahaitouf
Keyword(s):  
High Speed ◽  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Soft Decision ◽  
Ldpc Decoding ◽  
Low Density Parity Check ◽  
Dsp Implementation ◽  
Hard Decision ◽  
Decision Algorithms

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms.  In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF).  An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>

scholarly journals High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

2021 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Ldpc Codes ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Chip Area ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
The One

<p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.</p>

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