A New Clock Synchronization Method for Multi-FPGA Systems

2011 ◽  
Vol 204-210 ◽  
pp. 907-910
Author(s):  
Cheng Chang Zhang ◽  
Li Sheng Yang ◽  
Xiao Ping Hu ◽  
Hong Yang ◽  
Ping Li

A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.

2013 ◽  
Vol 333-335 ◽  
pp. 472-479
Author(s):  
Jian Fei An ◽  
Ke Zhu Song ◽  
Lin Feng Shang ◽  
Jun Feng Yang

In land seismic data acquisition systems, as seismic exploration goes towards to cover large area, a multi-channel structure is needed. In such systems, synchronization is very important, which has great influence on data acquisition and transmission. In this paper, a clock synchronization scheme for seismic exploration is proposed. In the scheme, LVDS serial transmission is used so that the whole system clocks can be made to have the same frequency through clock data recovery technique. Moreover, to compensate the effect caused by transmission delay, an effective algorithm based on PLL phase locked and FPGA logic is proposed in this scheme. The test results show that this scheme meets the system clock synchronization requirements well with the error precision less than 1ns, which fully demonstrates the feasibility and reliability of the scheme. The scheme proposed here can be used in related systems which require clock synchronization.


2021 ◽  
Vol 1744 (4) ◽  
pp. 042195
Author(s):  
Qin Mei ◽  
Yisheng Wang ◽  
Ting Wang ◽  
Xing Tong

Author(s):  
Juan Zhou ◽  
Jincheng Li ◽  
Haibo Zhong ◽  
Xudong Shi ◽  
Ge Yang ◽  
...  

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