A New Clock Synchronization Method for Multi-FPGA Systems
2011 ◽
Vol 204-210
◽
pp. 907-910
Keyword(s):
A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.
2013 ◽
Vol 333-335
◽
pp. 472-479
2021 ◽
Vol 1744
(4)
◽
pp. 042195
2012 ◽
pp. 246-254
◽
2021 ◽
Vol 68
(1)
◽
pp. 136-142