Researches on Channel Mismatch Effects in Time-Interleaved ADC System

2013 ◽  
Vol 655-657 ◽  
pp. 978-983
Author(s):  
Hui Yong Sun ◽  
Peng Cao
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Mismatch Error ◽  
Signal To Noise ◽  
Gain Error ◽  
Channel Mismatch ◽  
High Speed Data Acquisition ◽  
Interleaved Adc ◽  
Time Interleaved

The Time-Interleaved ADC（TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the tolerance range of TIADC channel mismatch error. Meanwhile, the result of this paper has provided a theoretical basis for eliminating TIADC channel mismatch error.

NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

2004 ◽  
Vol 13 (06) ◽  
pp. 1183-1201
Author(s):  
KAMAL EL-SANKARY ◽  
ALI ASSI ◽  
MOHAMAD SAWAN
Keyword(s):  
High Speed ◽  
Sampling Method ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Wireless Transceiver ◽  
Spurious Free Dynamic Range ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Free Dynamic

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

An Over 120dB Dynamic Range Linear Response Single Exposure CMOS Image Sensor with Two-stage Lateral Overflow Integration Trench Capacitors

2020 ◽  
Vol 2020 (7) ◽  
pp. 143-1-143-6 ◽  
Author(s):  
Yasuyuki Fujihara ◽  
Maasa Murata ◽  
Shota Nakayama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa
Keyword(s):  
Linear Response ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Signal To Noise ◽  
Single Exposure ◽  
Two Stage ◽  
Noise Ratio ◽  
Maximum Signal

This paper presents a prototype linear response single exposure CMOS image sensor with two-stage lateral overflow integration trench capacitors (LOFITreCs) exhibiting over 120dB dynamic range with 11.4Me- full well capacity (FWC) and maximum signal-to-noise ratio (SNR) of 70dB. The measured SNR at all switching points were over 35dB thanks to the proposed two-stage LOFITreCs.

Time-Interleaved ADC Gain Mismatch Calibration in High-Speed OFDM Systems

2021 ◽  
Author(s):  
Vo Trung Dung Huynh ◽  
Mai Linh ◽  
Minh N.T. Nguyen ◽  
Hien Ta ◽  
Duc Trung Nguyen
Keyword(s):  
High Speed ◽  
Ofdm Systems ◽  
Interleaved Adc ◽  
Time Interleaved

BANDWIDTH OF THE RECEIVER OF DIGITAL SIGNALS WITH A LARGE DYNAMIC RANGE

2021 ◽  
Vol 0 (11) ◽  
Author(s):  
A. E. Denisov ◽  
◽  
D. P. Danilaev ◽  
G. I. Il'in ◽  
◽  
...  
Keyword(s):  
Communication Channel ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Digital Signals ◽  
Resolution Time ◽  
Large Dynamic Range ◽  
Signal To Noise ◽  
Radio Engineering ◽  
Channel Parameters ◽  
Analytical Relations

The analysis of the connection between the bandwidth and the dynamic range, the signal-to-noise ratio, the resolution time and the bandwidth is carried out. The problems are solved by deriving analytical dependencies based on the Shannon – Hartley theorem, as well as the well-known postulates of the theory of radio engineering circuits and signals. The study of analytical relations allows us to identify restrictions on the choice of communication channel parameters.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

Study on the measurement speed and signal to noise ratio of multi tone burst wave for high speed non-contact acoustic inspection method

2016 ◽  
Vol 140 (4) ◽  
pp. 3212-3212
Author(s):  
Nobuaki Kosuge ◽  
Tsuneyosi Sugimoto ◽  
Kazuko Sugimoto ◽  
Chitose Kuroda ◽  
Noriyuki Utagawa
Keyword(s):  
High Speed ◽  
Signal To Noise Ratio ◽  
Tone Burst ◽  
Signal To Noise ◽  
Inspection Method ◽  
Noise Ratio ◽  
Acoustic Inspection
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