Low Voltage Low Power Up-Conversion Mixer for Wireless Sensor Networks Node Application

2013 ◽  
Vol 760-762 ◽  
pp. 516-520
Author(s):  
Ge Sun ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Wireless Sensor ◽  
Operating Voltage ◽  
Conversion Gain

A low voltage, low power up-conversion mixer is presented here for 2.4GHz wireless sensor networks (WSN). It was based on a double-balanced Gilbert cell type. The current-reuse technique was used to reduce the power consumption and negative-resistance compensation technique was used to improve the conversion gain. The mixer was designed in 0.18μm RF CMOS technology, and was simulated with Cadence SpectreRF. The simulation results indicate that the conversion gain is 6.37dB, the noise figure is 15.36dB and the input 1dB compression point is-10.3dBm, while consuming 1mA current for operating voltage at 1V.

Highly Integrated Ultra-Low Power RF Transceivers for Wireless Sensor Networks

2018 ◽  
pp. 14-1-14-23
Author(s):  
Brian P. Otis ◽  
Yuen Hui Chee ◽  
Richard Lu ◽  
Nathan M. Pletcher ◽  
Jan M. Rabaey ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Wireless Sensor ◽  
Ultra Low Power ◽  
Rf Transceivers

scholarly journals Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6111
Author(s):  
Sangjun Lee ◽  
Kyunghwan Cho ◽  
Jihye Kim ◽  
Jongho Park ◽  
Inhwan Lee ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Power Reduction ◽  
Wireless Sensor ◽  
Computational Time ◽  
Test Power ◽  
Significant Power ◽  
Highly Correlated ◽  
Scan Chain

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.

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