Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

A Feed-Forward Sigma-Delta Modulator Applied in Silicon Gyroscope

2015 ◽  
Vol 645-646 ◽  
pp. 657-661
Author(s):  
Qi Shao ◽  
Qiu Ye Lv ◽  
Hao Meng ◽  
Qiang Fu ◽  
Xiao Wei Liu
Keyword(s):  
Sampling Rate ◽  
Ideal Model ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Signal Band

Aiming to be applied in silicon gyroscope, a three-order single loop feedforward modulator with three-bit quantizer and local feedback is designed in this paper. Signal band is 200 KHz, sampling rate is 25.6 MHz, OSR is 64. Ideal modulator is then designed and simulated in MATLAB, getting SNR 125dB. Non-ideal factors are also added to ideal model, DWA technology is adopted to restrain the nonlinearity of multi-bit quantizer, getting SNR 104dB. Finally, transistor-level full-difference modulator is designed and simulated in Cadence, fetting SNR 101.3dB.

Single-loop sigma delta modulator design and verification for cognitive IoT applications

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Vamsee Krishna S. ◽  
Sudhakara Reddy P. ◽  
Chandra Mohan Reddy S.
Keyword(s):  
Discrete Time ◽  
Noise Shaping ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Content Type ◽  
Power Efficient ◽  
Single Loop ◽  
Physiological Signal ◽  
Iot Applications

Purpose A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz. Design/methodology/approach This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications. Findings The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping. Originality/value This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

Stable boundaries of a third-order sigma-delta modulator

2003 ◽  
Author(s):  
J. Zhang ◽  
P.V. Brennan ◽  
D. Jiang ◽  
E. Vinogradova ◽  
P.D. Smith
Keyword(s):  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

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