Modeling and System-Level Computer Simulation Approach for Optimization of Single-Loop CT Sigma Delta ADC

2018 ◽  
pp. 339-347
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G. R. Sinha
Keyword(s):  
Computer Simulation ◽  
System Level ◽  
Simulation Approach ◽  
Sigma Delta ◽  
Single Loop ◽  
Sigma Delta Adc

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

scholarly journals Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter

2016 ◽  
Vol 4 (3) ◽  
pp. 85-90
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
System Level ◽  
Dynamic Parameters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Matlab Simulink ◽  
Analog To Digital ◽  
System Level Modeling ◽  
Self Test ◽  
Sigma Delta Adc

System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope

2015 ◽  
Vol 645-646 ◽  
pp. 548-554
Author(s):  
Fu Xiang Huang ◽  
Zhi Qiang Gao ◽  
Xiao Wei Liu
Keyword(s):  
System Level ◽  
Noise Shaping ◽  
Ideal Model ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Fully Differential ◽  
Switch Capacitor ◽  
Partial Feedback ◽  
Sigma Delta Adc ◽  
The Ideal

Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

scholarly journals Analysis of Quantization Noise and Power Estimation of Continuous-Time Delta Sigma Analog-to-Digital Converter Using Test Enable Feature For 4G Radios

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
Low Voltage ◽  
Quantization Noise ◽  
System Level ◽  
Sigma Delta ◽  
Radio System ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Novel Approach ◽  
Delta Sigma ◽  
Sigma Delta Adc

<span>This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied</span><span lang="IN">.</span>

A High-Performance Fourth-Order Sigma-Delta Micromachined Accelerometer

2011 ◽  
Vol 483 ◽  
pp. 422-426
Author(s):  
Yao Guang Li ◽  
Xiao Wei Liu ◽  
Yan Xiao ◽  
Yun Tao Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
Quantization Noise ◽  
System Level ◽  
Sensing Element ◽  
Sigma Delta ◽  
Single Loop ◽  
System Level Simulation ◽  
Locus Method ◽  
Σδ Modulator

This paper reports on a system level design and analysis of a single-loop fourth-order sigma-delta (ΣΔ) accelerometer. Compared with a second-order single-loop ΣΔ modulator (ΣΔM) formed by the sensing element here the sensing element is cascaded with two extra electronic integrators to form the fourth ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 96.86 dB, and the effective number of bits (ENOB) is 15.8 bits when the over sampling ratio (OSR) is 128. Stability of the system is analyzed by root locus method based on the linear model established in this work, and the minimum gain of the quantizer Kq min is about 0.375.

Sigma-Delta ADC on SOI Technology for Working at High Temperatures

2020 ◽  
Vol 63 (11) ◽  
pp. 586-595
Author(s):  
Alexander Korotkov ◽  
Dmitry Morozov ◽  
Mikhail Pilipko ◽  
Mikhail Yenuchenko
Keyword(s):  
High Temperatures ◽  
Sigma Delta ◽  
Sigma Delta Adc ◽  
Soi Technology
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