4H-SiC Trench Structure Fabrication with Al2O3 Etching Mask

Trench structure etching is one of the most important processes for the fabrication of 4H-SiC Trench MOSFETs. This paper introduced Al2O3 as an etching mask for the fabrication of trench structures. The effect of dry etching parameters to the shape of trench structures were studied systematically. Micro trenches were successfully eliminated from trench structure etching process and preliminary trench MOSFET test structures were fabricated and characterized.

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Failure Analysis and Process Improvement for Through Silicon Via Interconnects

MRS Proceedings ◽

10.1557/proc-1156-d08-04-f06-04 ◽

2009 ◽

Vol 1156 ◽

Cited By ~ 4

Author(s):

Bivragh Majeed ◽

Marc Van Cauwenberghe ◽

Deniz Sabuncuoglu Tezcan ◽

Philippe Soussan

Keyword(s):

Failure Analysis ◽

Process Improvement ◽

Etching Rate ◽

Dry Etching ◽

Etching Process ◽

Thickness Variation ◽

Silicon Etching ◽

Soft Landing ◽

Etching Profile ◽

Etching Parameters

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

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Erratum: Dry etching process for fabrication of optoelectronic gratings in III-V substrates

Electronics Letters ◽

10.1049/el:19920212 ◽

1992 ◽

Vol 28 (3) ◽

pp. 338

Author(s):

A.S. Gozdz ◽

J.A. Shelburne ◽

R.S. Robinson ◽

C.C. Chang

Keyword(s):

Dry Etching ◽

Etching Process

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Low-temperature smoothing method of scalloped DRIE trench by post-dry etching process based on SF6 plasma

Micro and Nano Systems Letters ◽

10.1186/s40486-020-00116-x ◽

2020 ◽

Vol 8 (1) ◽

Author(s):

Jin Soo Park ◽

Dong-Hyun Kang ◽

Seung Min Kwak ◽

Tae Song Kim ◽

Jung Ho Park ◽

...

Keyword(s):

Low Temperature ◽

Dry Etching ◽

Smoothing Method ◽

Etching Process

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Grain size reduction by utilizing a very thin CrW seedlayer and dry-etching process in CoCrTaNiPt longitudinal media

Journal of Applied Physics ◽

10.1063/1.372866 ◽

2000 ◽

Vol 87 (9) ◽

pp. 6860-6862 ◽

Cited By ~ 14

Author(s):

Satoru Yoshimura ◽

D. D. Djayaprawira ◽

Tham Kim Kong ◽

Yusuke Masuda ◽

Hiroki Shoji ◽

...

Keyword(s):

Grain Size ◽

Dry Etching ◽

Size Reduction ◽

Etching Process

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Dry Etching of Germanium with Laser Induced Reactive Micro Plasma

Lasers in Manufacturing and Materials Processing ◽

10.1007/s40516-021-00147-1 ◽

2021 ◽

Author(s):

Martin Ehrhardt ◽

Pierre Lorenz ◽

Jens Bauer ◽

Robert Heinke ◽

Mohammad Afaque Hossain ◽

...

Keyword(s):

Ion Beam ◽

Etching Rate ◽

Dry Etching ◽

Etching Process ◽

High Tech ◽

Etching Time ◽

High Quality ◽

Machined Surface ◽

Reactive Plasma ◽

New Processing

AbstractHigh-quality, ultra-precise processing of surfaces is of high importance for high-tech industry and requires a good depth control of processing, a low roughness of the machined surface and as little as possible surface and subsurface damage but cannot be realized by laser ablation processes. Contrary, electron/ion beam, plasma processes and dry etching are utilized in microelectronics, optics and photonics. Here, we have demonstrated a laser-induced plasma (LIP) etching of single crystalline germanium by an optically pumped reactive plasma, resulting in high quality etching. A Ti:Sapphire laser (λ = 775 nm, EPulse/max. = 1 mJ, t = 150 fs, frep. = 1 kHz) has been used, after focusing with a 60 mm lens, for igniting a temporary plasma in a CF4/O2 gas at near atmospheric pressure. Typical etching rate of approximately ~ 100 nm / min and a surface roughness of less than 11 nm rms were found. The etching results were studied in dependence on laser pulse energy, etching time, and plasma – surface distance. The mechanism of the etching process is expected to be of chemical nature by the formation of volatile products from the chemical reaction of laser plasma activated species with the germanium surface. This proposed laser etching process can provide new processing capabilities of materials for ultra—high precision laser machining of semiconducting materials as can applied for infrared optics machining.

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