scholarly journals Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

2014 ◽  
Vol 108 (14) ◽  
pp. 29-34
Author(s):  
A. Ranganayakulu ◽  
K. Satyaprasad
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Data Driven ◽  
Clock Gating ◽  
Low Power Vlsi Design ◽  
Gating Scheme

Low-Power VLSI Design: An Overview

1995 ◽  
pp. 1-12
Author(s):  
Abdellatif Bellaouar ◽  
Mohamed I. Elmasry
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Low Power Vlsi Design

Low-power VLSI design of arithmetic and logic circuits using the multiple-threshold CMOS technique

2021 ◽  
pp. 624-632
Author(s):  
Prachi Kataria ◽  
Anuwarti Rai ◽  
Aanchal Singh ◽  
Ashwin Anand ◽  
Raman Kapoor ◽  
...  
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Multiple Threshold ◽  
Low Power Vlsi Design
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