Flash Translation Layer for Heterogeneous NAND Flash-based Storage Devices Based on Access Patterns of Logical Blocks

2013 ◽  
Vol 50 (5) ◽  
pp. 94-101
Author(s):  
Kwanhu Bang ◽  
Sang-Hoon Park ◽  
Hyuk-Jun Lee ◽  
Eui-Young Chung
Keyword(s):  
Nand Flash ◽  
Storage Devices ◽  
Flash Translation Layer ◽  
Access Patterns

PCI Express-Based NVMe Solid State Disk

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Detailed Design ◽  
Pci Express ◽  
Storage Media ◽  
Solid State Disk ◽  
Memory Card ◽  
Non Volatile Memory ◽  
Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

scholarly journals Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices

Sensors ◽  
2020 ◽  
Vol 20 (10) ◽  
pp. 2952 ◽  
Author(s):  
Seung-Ho Lim ◽  
Ki-Woong Park
Keyword(s):  
Flash Memory ◽  
Error Recovery ◽  
Recovery Phase ◽  
Error Correction Codes ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Storage ◽  
Storage Devices ◽  
Complementary Method ◽  
Compressed Data

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

scholarly journals High‐efficient superblock flash translation layer for NAND flash controller

2020 ◽  
Vol 56 (6) ◽  
pp. 278-280
Author(s):  
Peiyong Zhang ◽  
Huanjie Tang
Keyword(s):  
Nand Flash ◽  
High Efficient ◽  
Flash Translation Layer

An Efficient Flash Translation Layer for Large Block NAND Flash Devices

2015 ◽  
Vol 24 (09) ◽  
pp. 1550138 ◽  
Author(s):  
Tae-Sun Chung ◽  
Dong-Joo Park ◽  
Jongik Kim
Keyword(s):  
Flash Memory ◽  
System Performance ◽  
Smart Phones ◽  
Large Block ◽  
Nand Flash ◽  
Digital Cameras ◽  
Key Factor ◽  
Mp3 Players ◽  
Flash Translation Layer ◽  
Embedded Applications

Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices

2014 ◽  
Vol 63 (5) ◽  
pp. 1085-1096 ◽  
Author(s):  
Sang-Hoon Park ◽  
Dong-gun Kim ◽  
Kwanhu Bang ◽  
Hyuk-Jun Lee ◽  
Sungjoo Yoo ◽  
...  
Keyword(s):  
Idle Time ◽  
Low Latency ◽  
Nand Flash ◽  
Storage Devices
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