On line self recovery of embedded multi-processor SOC on FPGA using dynamic partial reconfiguration

2012 ◽  
Vol 41 (2) ◽  
Author(s):  
Uros Legat ◽  
Anton Biasizzo ◽  
Franc Novak
Keyword(s):  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
On Line

scholarly journals Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

2018 ◽  
Vol 6 (3) ◽  
pp. 160
Author(s):  
G. Prasad Acharya ◽  
M. Asha Rani
Keyword(s):  
Experimental Setup ◽  
Partial Reconfiguration ◽  
Core System ◽  
Dynamic Partial Reconfiguration ◽  
Test Setup ◽  
Hardware Overhead ◽  
On Line ◽  
Line Test ◽  
Simulation Results ◽  
Evaluation Board

<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>

Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments

2017 ◽  
Author(s):  
Alexander Dorflinger ◽  
Bjorn Fiethe ◽  
Harald Michalik ◽  
Sandor P. Fekete ◽  
Phillip Keldenich ◽  
...  
Keyword(s):  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Space Instruments
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