scholarly journals A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor

2014 ◽  
Vol 18 (1) ◽  
pp. 129-134
Author(s):  
Yeon-Ho Jeong ◽  
Young-Chan Jang
Keyword(s):  
Analog To Digital Converter ◽  
Digital Converter ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Analog Converter ◽  
Digital To Analog ◽  
Asynchronous Sar

scholarly journals Design of high-resolution digital-to-analog converter for 14-bit successive approximation analog-to-digital converter

2020 ◽  
Vol 1529 ◽  
pp. 052101
Author(s):  
Muhammad Syafiee Kamaruzaman ◽  
Nabihah Ahmad ◽  
Siti Hawa Ruslan ◽  
Hasmayadi Abdul Majid ◽  
C Y Chia ◽  
...  
Keyword(s):  
High Resolution ◽  
Successive Approximation ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Analog Converter ◽  
Digital To Analog

scholarly journals Development of Heavy Metal Potentiostat for Batik Industry

2020 ◽  
Vol 10 (21) ◽  
pp. 7804
Author(s):  
Siti Nur Hanisah Umar ◽  
Mohammad Nishat Akhtar ◽  
Elmi Abu Bakar ◽  
Noorfazreena M. Kamaruddin ◽  
Abdul Rahim Othman
Keyword(s):  
Heavy Metal ◽  
Reactive Dyes ◽  
Digital Converter ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Accuracy Test ◽  
Analog Converter ◽  
Circuit Component ◽  
Scale Design ◽  
Precision Rate

The consumption of reactive dyes in the batik industry has led to a severe concern in monitoring the heavy metal level in wastewater. Due to the necessity of implementing a wastewater monitoring system in the batik factory, a Heavy Metal potentiostat (HMstat) was designed. The main goal of this study is to understand the optimal design concept of the potentiostat function in order to investigate the losses of accuracy in measurement using off-the-shelf devices. Through lab-scale design, the HMstat comprises of an analog potentiostat read-out circuit component (PRCC) and a digital control signal component (CSC). The PRCC is based on easy to use components integrated with a NI-myRIO controller in a CSC. Here, the myRIO was equipped with built-in analog to digital converter (ADC) and digital to analog converter (DAC) components. In this paper, the accuracy test and detection of cadmium(II) (Cd2+) and lead(II) (Pb2+) were conducted using the HMstat. The results were compared with the Rodeostat (an open source potentiostat available on the online market). The accuracy of the HMStat was higher than 95% and within the precision rate of the components used. The HMstat was able to detect Cd2+ and Pb2+ at −0.25 and −0.3 V, respectively. Similar potential peaks were obtained using Rodeostat (Cd2+ at −0.25 V and Pb2+ at −0.3 V).

scholarly journals A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Clock Generation ◽  
Analog Converter ◽  
Asynchronous Sar

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

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