scholarly journals Development of Heavy Metal Potentiostat for Batik Industry

2020 ◽  
Vol 10 (21) ◽  
pp. 7804
Author(s):  
Siti Nur Hanisah Umar ◽  
Mohammad Nishat Akhtar ◽  
Elmi Abu Bakar ◽  
Noorfazreena M. Kamaruddin ◽  
Abdul Rahim Othman
Keyword(s):  
Heavy Metal ◽  
Reactive Dyes ◽  
Digital Converter ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Accuracy Test ◽  
Analog Converter ◽  
Circuit Component ◽  
Scale Design ◽  
Precision Rate

The consumption of reactive dyes in the batik industry has led to a severe concern in monitoring the heavy metal level in wastewater. Due to the necessity of implementing a wastewater monitoring system in the batik factory, a Heavy Metal potentiostat (HMstat) was designed. The main goal of this study is to understand the optimal design concept of the potentiostat function in order to investigate the losses of accuracy in measurement using off-the-shelf devices. Through lab-scale design, the HMstat comprises of an analog potentiostat read-out circuit component (PRCC) and a digital control signal component (CSC). The PRCC is based on easy to use components integrated with a NI-myRIO controller in a CSC. Here, the myRIO was equipped with built-in analog to digital converter (ADC) and digital to analog converter (DAC) components. In this paper, the accuracy test and detection of cadmium(II) (Cd2+) and lead(II) (Pb2+) were conducted using the HMstat. The results were compared with the Rodeostat (an open source potentiostat available on the online market). The accuracy of the HMStat was higher than 95% and within the precision rate of the components used. The HMstat was able to detect Cd2+ and Pb2+ at −0.25 and −0.3 V, respectively. Similar potential peaks were obtained using Rodeostat (Cd2+ at −0.25 V and Pb2+ at −0.3 V).

scholarly journals A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1100
Author(s):  
Deeksha Verma ◽  
Khuram Shehzad ◽  
Danial Khan ◽  
Sung Jin Kim ◽  
Young Gun Pu ◽  
...  
Keyword(s):  
Low Power ◽  
Sampling Rate ◽  
Complementary Metal Oxide Semiconductor ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Clock Generation ◽  
Analog Converter ◽  
Asynchronous Sar

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

A Noise Reduction 12-bit 125-MSPS SAR ADC with Modified Asynchronous Logic Regulation Technique

2020 ◽  
pp. 2150040
Author(s):  
Daiguo Xu ◽  
Han Yang ◽  
Xing Sheng ◽  
Ting Sun ◽  
Guangbing Chen ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Feedback Loop ◽  
Cmos Technology ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Asynchronous Logic ◽  
Analog Converter ◽  
Nyquist Rate

This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165[Formula: see text][Formula: see text]V rms at 60∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4[Formula: see text]mW from 1.2[Formula: see text]V power supply with a [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.048[Formula: see text]mm2, and the corresponding FoM is 27.2[Formula: see text]fJ/conversion-step at Nyquist rate.

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