scholarly journals A Novel SVPWM Algorithm Considering Neutral - Point Potential Balancing for Three - Level NPC Inverter

2017 ◽  
Vol 20 (2) ◽  
pp. 69
Author(s):  
Chen Yongchao ◽  
Li Yanda ◽  
Zhao Ling

For three-level inverter, complexity of control strategy and neutral-point potential imbalance problem of DC side is the bottleneck restricting its application. In order to solve the problem, a simplified implementation of three- level space vector pulse width modulation (SVPWM) considering neutral-point potential balancing is proposed in this paper. The proposed SVPWM algorithm is based on judging of three phase voltages and voltage-second balance principle, which does not need to perform the sine and cosine c alculations, and thus it is more convenient and effective than traditional SVPWM algorithm. Also, the neutral-point potential balancing can be realized conveniently and effectively. The proposed algorithm can not only effectively simplify the calculation and reduce calculation time greatly, but also achieve the same control effect as traditional SVPWM. It has certain reference significance and can be used to shorten sampling time and improve the inverter performance. Finally, the proposed SVPWM algorithm is verified by simulation and experimental results.

Energies ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 4328 ◽  
Author(s):  
Yunlei Zhang ◽  
Cungang Hu ◽  
Qunjing Wang ◽  
Yufei Zhou ◽  
Yue Sun

A selective harmonic elimination pulse width modulation (SHEPWM) control strategy is proposed to balance the neutral-point potential (NP) of a three-level active neutral-point-clamped (ANPC) converter. In this strategy, the chaotic ant colony algorithm (ACA) is adopted to solve the SHEPWM nonlinear equations, which does not require presetting the initial values of solutions and can get multiple solutions in the same modulation index. The influence of different solutions corresponding to the SHEPWM switching states on the NP is different, namely, some make the NP increase and others make the NP decrease. Therefore, the NP balancing can be effectively controlled by choosing appropriate solutions in different fundamental periods. The simulation and experimental results further verify the feasibility and effectiveness of the control strategy.


2018 ◽  
Vol 2018 ◽  
pp. 1-9
Author(s):  
Yanxia Shen ◽  
Beibei Miao ◽  
Dinghui Wu ◽  
Kader Ali Ibrahim

A fault-tolerant control technique is discussed for the Neutral-Point-Clamped (NPC) three-level inverter, which ensures that the NPC inverter operates normally even under device failures. A two-level leg is added to the NPC inverter; when the device open circuit fault occurs, the load of this faulty phase is connected to the neutral point of this two-level leg through the bidirectional thyristors. An improved Space Vector Pulse Width Modulation (SVPWM) strategy called “addition and subtraction substitution SVPWM” is proposed to effectively suppress fluctuation in capacitor neutral-point voltages by readjusting the sequence and action time of voltage vectors. The fault-tolerant topology in this paper has the advantages of fewer switching devices and lower circuit costs. Experimental results show that the proposed fault-tolerant system can operate in balance of capacitor neutral-point voltages at full output power and the reliability of the inverter is greatly enhanced.


Energies ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 779 ◽  
Author(s):  
Ming Wu ◽  
Zhenhao Song ◽  
Zhipeng Lv ◽  
Kai Zhou ◽  
Qi Cui

To suppress the direct current (DC) capacitor voltage fluctuations and the common-mode voltage (CMV) in a three-phase, five-level, neutral-point-clamped (NPC)/H-bridge inverter, this paper analyzes the influence of all voltage vectors on the neutral point potential of each phase under different pulse mappings in detail with an explanation of the CMV distribution. Then, based on the traditional space vector pulse width modulation (SVPWM) algorithm, a dual-pulse-mapping algorithm is proposed to suppress the DC capacitor fluctuations and the CMV simultaneously. In the algorithm, the reference voltage synthesis selects the voltage vector that has the smallest CMV value as the priority. In addition, the two kinds of pulse mappings that have opposite effects on the neutral point potential are switched to output. At the same time, regulating factors are introduced to adjust the working time of each voltage vector under the two pulse mappings; then, the capacitor voltages can be balanced. Both the simulation and experiment demonstrate the algorithm’s effectiveness.


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