The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.
Exploiting on-chip inductance in high speed clock distribution networks