Broadband On-Chip Transmission Line Characterization Used in High-Speed and High-Frequency Communications

2021 ◽  
Author(s):  
Chien-Chang Huang ◽  
Wen-Tsao Fu ◽  
Kuan-Chien Cheng
Keyword(s):  
Transmission Line ◽  
High Frequency ◽  
High Speed ◽  
On Chip

scholarly journals Thermal Efficient Design of Distributed MemorGenerator for Dual-port RAM Using Unidirectional High-performance IO Standard

2018 ◽  
Vol 34 (2) ◽  
Author(s):  
B. DAS ◽  
M.F.L. ABDULLAH
Keyword(s):  
High Frequency ◽  
High Speed ◽  
Data Rate ◽  
Sleep Mode ◽  
Chip Temperature ◽  
Rate Transmission ◽  
High Frequency Operation ◽  
On Chip ◽  
Data Rate Transmission ◽  
Slave Mode

he distributeddual-port RAM offersthe high-speed data rate transmission for differentmemory access modes such as: busy mode; interrupt mode; JTAG mode; maser mode; slave mode; and sleep mode, at high-frequency operation. The execution of these modes at high-frequency operation increases the on-chip temperature of distributeddual-port RAM. It might short the distribute dual-port RAM forever. Currently, differenttechniques have been reported, but significanton-chip temperature consumption is not reduced for distributeddual-port RAM. In this paper, the thermal-efficiendesign for disributed dual-port RAM was achieved using IO sandard technique. The distributeddual-port RAM was designed using differentIO standardssuch as; LVTTL IO standardand Mobile_DDR IO standard.It was determined that distributeddual-port RAM was operated at 625 MHz high-frequency operation for busy mode, interrupt mode, JTAG mode, mastermode, slave mode, and sleep mode using LVTTL IO standardand Mobile_DDR IO standard.It was observed that for busy mode 53%, for interrupt mode 61%, for JTAG mode 68%, for mastermode 62%, for slave mode 59%, and for sleep mode 76% temperature was reduced when distrbuted dual-port RAM was designed using Mobile_DDR IO stndard compared to LVTTL IO stndard. The designed distributd dual-port RAM using Mobile_DDR IO stndard offerd the thermal efficiendesign solution for differentmemory access modes at high-frequency data rate transmission that provided the low on-chip temperature consumption. The developed distibuted dual-port RAM will be helpful to produce green computing devices.

INTEGRATED SiGe AND Si DEVICE CAPABILITIES AND TRENDS FOR MULTI-GIGAHERTZ APPLICATIONS

2003 ◽  
Vol 13 (01) ◽  
pp. 175-219 ◽  
Author(s):  
G. G. FREEMAN ◽  
B. JAGANNATHAN ◽  
N. ZAMDMER ◽  
R. GROVES ◽  
R. SINGH ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
High Frequency ◽  
High Speed ◽  
Very High Frequency ◽  
Silicon Photodiode ◽  
Sige Hbt ◽  
Wide Range ◽  
On Chip ◽  
Silicon Based ◽  
Very High

Silicon-based devices, including the increasingly available SiGe-based devices, are now demonstrating fT and fMAX values over 200 GHz. These recent advances open the door to a wide range of silicon-based very high frequency, low power and highly integrated solutions. Trends in silicon MOS, SiGe HBT, SiGe MODFET and SiGe strained silicon FETs are reported. Silicon inroads to device functions viewed as the sole realm of III-V technologies are also being demonstrated. Capability and trends of the integrated silicon photodiode are reported here as an example. Integration of these high-speed devices into a complex circuit requires on-chip passive device functionality at such high frequency. Key devices to enable integration are the inductor, varactor, and transmission line, and operation of these devices at high frequency is reported. Further, we discuss noise isolation issues and techniques, which may be used when minimizing cross-talk within a conductive silicon substrate.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Couplinator: A simple computational tool for synthesis of multi-section coupled-line filter based on MPCM-TLM technique

2021 ◽  
pp. 1-10
Author(s):  
E. Faghand ◽  
S. Karimian ◽  
E. Mehrshahi ◽  
N. Karimian
Keyword(s):  
Comparative Analysis ◽  
Transmission Line ◽  
High Frequency ◽  
Computational Tool ◽  
Cad Tools ◽  
Coupled Line ◽  
High Frequency Structure Simulator ◽  
Transmission Line Method ◽  
Set Up ◽  
Planar Circuit

Abstract A new simple computational tool is proposed for the synthesis of multi-section coupled-line filters based on combined modified planar circuit method (MPCM) and transmission line method (TLM) analysis, referred to as MPCM-TLM. Due to its fundamentally simple architecture, the presented tool offers significantly faster optimization of coupled-line filters – for exactly the same initial simulation set-up – than other costly commercially-available tools, giving equally reliable results. Validity and accuracy of the proposed tool have been verified through the design of 3rd, 5th, and 7th order coupled-line filters and comparative analysis between results obtained from the proposed approach and the high-frequency structure simulator. A remarkable 99% time reduction in the analysis is recorded in the case of 7th order filter using the proposed tool, for almost identical results to HFSS. Therefore, it can be confidently claimed that the proposed technique can be used as a reliable alternative to existing complex, costly, processor-intensive CAD tools.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

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