High-performance Block Cipher Using Flexible Architecture

2021 ◽  
Vol 6 (1) ◽  
pp. 188-193
Author(s):  
Dr.V.J. Arulkarthick
Keyword(s):  
High Performance ◽  
Block Cipher ◽  
Critical Path ◽  
Tree Structure ◽  
Light Weight ◽  
Contemporary World ◽  
Flexible Architecture ◽  
Parallel Prefix ◽  
Prefix Adder

Light weight cryptography has been a prominent sector in exploring the cryptanalytics in contemporary world. In this paper, an elevated production capable structure and pliant implementations of hardware by SPECK, which is a lightly weighted block cipher is presented. This lightly weighted SPECK can be accustomed to diminish the retardation of critical path, a tree structure for the realization of Sklansky adder which is an efficient parallel prefix adder operation is used.

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder

2020 ◽  
Vol 29 (12) ◽  
pp. 2050186
Author(s):  
Subodh Kumar Singhal ◽  
B. K. Mohanty ◽  
Sujit Kumar Patel ◽  
Gaurav Saxena
Keyword(s):  
Critical Path ◽  
Processing Unit ◽  
Path Delay ◽  
Core Component ◽  
The Core ◽  
Critical Path Delay ◽  
Parallel Prefix ◽  
Computation Algorithm ◽  
Logic Operations ◽  
Prefix Adder

Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

scholarly journals Design of High Speed Advanced Encryption Standard using PPA and PPM

2019 ◽  
Vol 8 (9) ◽  
pp. 2679-2684
Keyword(s):  
High Speed ◽  
Block Cipher ◽  
Internet Security ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Fundamental Goal ◽  
Parallel Prefix ◽  
Encoding Strategies ◽  
Prefix Adder ◽  
Symmetric Block

Basically, internet security plays crucial role in past three decades. So in worldwide Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. In this paper we proposed the simplified AES algorithm (S-DES) using parallel prefix adder (PPA) and parallel prefix multiplier (PPM). This parallel prefix adder and parallel prefix multiplier will generate a product formed by multiplying the multiplicand. This algorithm possess specific structure to encrypt and decrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, substitution, improvement and change encoding strategies. At last the key extension module will comprise the quantity of iterative preparing rounds so as to expand its resistance against unapproved assaults.

ARCHITECTURES AND FPGA IMPLEMENTATIONS OF THE 64-BIT MISTY1 BLOCK CIPHER

2006 ◽  
Vol 15 (06) ◽  
pp. 817-831 ◽  
Author(s):  
P. KITSOS ◽  
M. D. GALANIS ◽  
O. KOUFOPAVLOU
Keyword(s):  
Performance Improvement ◽  
High Performance ◽  
Block Cipher ◽  
Critical Path ◽  
Constrained Systems ◽  
Clock Frequency ◽  
Performance Requirements ◽  
Negative Edge

In this paper, we present two alternative architectures and FPGA implementations of the 64-bit NESSIE proposal, MISTY1 block cipher. The first architecture is suitable for applications with high-performance requirements. A throughput of up to 12.6 Gbps can be achieved at a clock frequency of 168 MHz. The main characteristic of this architecture is that uses RAM blocks embedded in modern FPGA devices in order to implement the S-boxes defined in the block cipher algorithm. The second architecture can be used in implementing applications on area-constrained systems. It utilizes feedback logic and inner pipeline with negative edge-triggered register. This technique shortens the critical path, without increasing the latency of the MISTY1 algorithm execution. Compared with an implementation without inner pipeline, performance improvement of 97% is achieved. The measured throughput of the second architecture implementation is 561 Mbps at 79 MHz.

Realization of Enhanced LMS Filter Using Carry Skip Adder And Quantum Dot Cellular Automation In VLSI For Removing Impulse Noises In Medical Image

2019 ◽  
Vol 14 ◽  
Author(s):  
K.R. Shankarkumar ◽  
Gokul Kumar
Keyword(s):  
Adaptive Filtering ◽  
Adaptive Filters ◽  
Pass Band ◽  
Least Mean Square ◽  
Low Pass ◽  
Parallel Prefix ◽  
Loop Feedback ◽  
Band Pass ◽  
The Difference ◽  
Prefix Adder

: Filtering is an important step in the field of image processing to suppress the required parts or to remove any artifacts present in it. There are different types of filters like low pass, high pass, Band pass, IIR, FIR and adaptive filtering etc.., in these filters adaptive filters is an important filter because it is used to remove the noisy signal and images. Least Mean Square filter is a type of an adaptive filtering which is used to remove the noises present in the medical images. The working of LMS is based on the minimization of the difference between the error images using a closed loop feedback. Therefore presented technique called as Q-CSKA. Here the CSKA performs its operation in stages which is based on the nucleus stage. In the traditional CSKA the nucleus stage is depend on the parallel prefix adder in this work it is replaced by the QCA adder. The QCA adder utilizes the less area compared to PPA and it can be realized in Nanometer range also. For multiplexers, And OR Invert, OR and Invert logic is used to reduce the area and delay. Due to these advantages of the QCA, AOI-OAI logic the proposed method outperformed the LMS implementation in area, power, and accuracy and delay, this based five type image noise of medical pictures related to the best technique is out comes. It helps to medicinal practitioner to resolve the symptoms of patient with ease.

Fused Ambipolar Aza-isoindigos with NIR absorption

2021 ◽  
Author(s):  
Liping Yao ◽  
Danlei Zhu ◽  
Hailiang Liao ◽  
Sheik Haseena ◽  
Mahesh kumar Ravva ◽  
...  
Keyword(s):  
Organic Semiconductors ◽  
High Performance ◽  
Low Cost ◽  
Light Weight ◽  
The Past ◽  
Pi Conjugated ◽  
Nir Absorption ◽  
Conjugated Organic Semiconductors

Due to their advantages of low-cost, light-weight, and mechanical flexibility, much attention has been focused on pi-conjugated organic semiconductors. In the past decade, although many materials with high performance has...

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