scholarly journals Design and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}

2021 ◽  
Vol 22 (1) ◽  
pp. 62
Author(s):  
Raj Kumar ◽  
Ram Awadh Mishra
Keyword(s):  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Magnitude Comparison ◽  
Power Efficient ◽  
Mixed Radix Conversion ◽  
Detection Circuit ◽  
Sign Detection ◽  
Parallel Prefix ◽  
Prefix Adder

Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo  {2<sup>n </sup>- 1, 2<sup>n</sup>, 2<sup>n</sup> + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.

scholarly journals Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder

2019 ◽  
Vol 9 (1) ◽  
pp. 3028-3031
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Propagation Delay ◽  
Main Role ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Parallel Prefix

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

Interval Estimation of Relative Values in Residue Number System

2017 ◽  
Vol 27 (01) ◽  
pp. 1850004 ◽  
Author(s):  
Konstantin Isupov ◽  
Vladimir Knyazkov
Keyword(s):  
High Speed ◽  
Interval Estimation ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Limiting Factor ◽  
Small Integer ◽  
Magnitude Comparison ◽  
Mixed Radix Conversion ◽  
Residue Number

Residue number system (RNS), due to its carry-free nature, is popular in many applications of high-speed computer arithmetic, especially in digital signal processing and cryptography. However, the main limiting factor of RNS is a high complexity of such operations as magnitude comparison, sign determination and overflow detection. These operations have, for many years, been a major obstacle to more widespread use of parallel residue arithmetic. This paper presents a new efficient method to perform these operations, which is based on computation and analysis of the interval estimation for the relative value of an RNS number. The estimation, which is called the interval floating-point characteristic (IFC), is represented by two directed rounded bounds that are fixed-precision numbers. Generally, the time complexities of serial and parallel computations of IFC are linear and logarithmic functions of the size of the moduli set, respectively. The new method requires only small-integer and fixed-precision floating-point operations and focuses on arbitrary moduli sets with large dynamic ranges ([Formula: see text]). Experiments indicate that the performance of the proposed method is significantly higher than that of methods based on Mixed-Radix Conversion.

A Scaler Design for the RNS Three-Moduli Set {2n+1−1,2n,2n−1} Based on Mixed-Radix Conversion

2019 ◽  
Vol 29 (03) ◽  
pp. 2050041 ◽  
Author(s):  
Ahmad Hiasat
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Scaling Factor ◽  
Vlsi Layout ◽  
Power Efficient ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Text Unit ◽  
Dsp Applications

Adopting the moduli set [Formula: see text] for different DSP applications instead of the traditional moduli set [Formula: see text] has the advantage of excluding modulus [Formula: see text]. A multiply-and-accumulate modulo [Formula: see text] unit is more demanding than a modulo [Formula: see text] unit, which signifies the importance of this adoption. This paper introduces a new design for a scaling unit “Scaler”, that deals with the arithmetic-friendly residue number system (RNS) moduli set [Formula: see text]. The scaling factor is the power-of-two moduli [Formula: see text]. The scaling algorithm is based on the mixed-radix conversion (MRC) technique, which converts RNS-based representation into a weighted representation. The proposed approach is compared with other functionally-identical or functionally-similar scalers that perform scaling for the same moduli set under consideration or for the moduli set [Formula: see text]. The comparison is carried using theoretical unit-gate approach and experimental VLSI layout approach. The proposed scaler is shown to be more area and power-efficient than recently published competitive works.

LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS

2007 ◽  
Vol 16 (02) ◽  
pp. 267-286 ◽  
Author(s):  
ALEXANDER SKAVANTZOS ◽  
MOHAMMAD ABDALLAH ◽  
THANOS STOURAITIS
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Chinese Remainder Theorem ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
New Class ◽  
Mixed Radix Conversion ◽  
Residue Number ◽  
Signal Processors

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS

2004 ◽  
Vol 13 (06) ◽  
pp. 1233-1249 ◽  
Author(s):  
WEI WANG ◽  
M. N. S. SWAMY ◽  
M. O. AHMAD
Keyword(s):  
Power Efficiency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Chinese Remainder Theorem ◽  
Low Cost ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Fpga Implementation ◽  
Fir Filters

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

2018 ◽  
Vol 57 (4) ◽  
pp. 361-375 ◽  
Author(s):  
J Jency Rubia ◽  
GA Sathish Kumar
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Large Scale ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Hardware Complexity ◽  
Logarithmic Number System ◽  
Logarithmic Number

The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

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