A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region

A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET.

High-performance SiC MOSFET embedded heterojunction diode with electric field protection region

In this study, we proposed high-performance SiC MOSFET embedded heterojunction diode (HJD) with an electric field protection (EFP) region and analyzed it using a Sentaurus TCAD simulation. The proposed device features an HJD positioned at the trench side wall in the middle of the JFET region and a highly doped EFP region under the P+ polysilicon to features excellent static performance and high reliability. The simulation results revealed that the maximum oxide electric field (EMOX) and the Baliga’s figure-of-merit (BFOM) improved by 54% and 12%, respectively, compared with those of conventional SiC MOSFETs (C-MOSFETs). In addition, the EFP region suppressed the DIBL effect and leakage current in the HJD interface sufficiently. The HJD suppressed the bipolar degradation of the PiN body diode effectively due to its low VF (1.75 V). In addition, the proposed device demonstrated superior reverse-recovery characteristics, thereby improving trr and Qrr by 35% and 57%, respectively, compared to the corresponding values in C-MOSFET. Moreover, the input capacitance (CISS) was reduced by 17.5%, and CGD was reduced by 96%. Therefore, the high-frequency figure-of-merit (HFOM) improved by a factor of 25.8 in terms of RON × CGD. As a result, the proposed device is a promising structure for high-frequency and high-reliability applications.