Оптимизация толщины слоя In-=SUB=-0.3-=/SUB=-Ga-=SUB=-0.7-=/SUB=-As в трехкаскадном In-=SUB=-0.3-=/SUB=-Ga-=SUB=-0.7-=/SUB=-As/GaAs/In-=SUB=-0.5-=/SUB=-Ga-=SUB=-0.5-=/SUB=-P солнечном элементе

The search of the optimal absorbing layer thickness in the bottom In0.3Ga0.7As subcell of the triple-junction In0.3Ga0.7As/GaAs/In0.5Ga0.5P solar cell was carried out assisted by the Sentaurus TCAD software package, depending on the minority charge carrier lifetime in this layer. The lifetime value was set manually and it was in the range from 17 ps to 53 ns. The calculation results showed that the optimal thickness varies from 0.9 to 7.5 μm. The estimation of the efficiency contribution of the bottom In0.3Ga0.7As subcell to the given triple-junction solar cell, at various lifetime values, was made. Its value varied from 1 to 7%.

INFLUENCE OF THE ALKALI SURFACE TREATMENTS ON THE INTERFACE-STATES DENSITY AND MINORITY CARRIER LIFETIME IN Cz–SILICON WAFER

The chemical etching of the surface of silicon wafers is a critical step in the manufacturing process of all semiconductor devices. In this contribution, we investigate the effect of alkaline etching on minority carrier lifetime and interface-states density ([Formula: see text] of silicon wafers intended to be used as solar cell substrates. After alkali treatment, the surface morphology was analyzed using scanning electron microscopy (SEM) and UV-visible-NIR optical spectroscopy. Besides and as electrical characterizations, the minority charge carrier lifetime ([Formula: see text] was measured by the Quasi-Steady State Photoconductance technique (QSSPC), and the Electrochemical Impedance Spectroscopy was used to evaluate [Formula: see text]. These results were correlated with the surface recombination velocity (SRV) calculated by fitting the experimental data to the theory. The results of characterization showed a lower SRV and a higher apparent lifetime ([Formula: see text] obtained with 23[Formula: see text]wt.% KOH etching as compared to those obtained with 30[Formula: see text]wt.% NaOH; viz. 825[Formula: see text]cm[Formula: see text] against 1500[Formula: see text]cm.s[Formula: see text] and 32[Formula: see text][Formula: see text]s against 23[Formula: see text][Formula: see text]s, respectively. These findings were corroborated by [Formula: see text] measurements which gave [Formula: see text][Formula: see text]ev[Formula: see text]cm[Formula: see text] for KOH treatment and [Formula: see text][Formula: see text]ev[Formula: see text]cm[Formula: see text] for NaOH treatment.

Surface Optimization of Random Pyramid Textured Silicon Substrates for Improving Heterojunction Solar Cells

Key steps in the fabrication of high-efficiency a-Si:H/c-Si heterojunction solar cells are the controlled pyramid texturing of the c-Si substrates to minimize reflection losses and the subsequent passivation by deposition of a high-quality a-Si:H layer to reduce recombination losses. This contribution reviews our recent results on the optimization of the wet-chemical texturing of crystalline Si wafers for the preparation of heterojunction solar cells with respect to low reflection losses, low recombination losses and long minority carrier lifetimes. It is demonstrated, that by joint optimization of both saw damage etch and texture etch the optical and electronic properties of the resulting pyramid morphology can be controlled. Effective surface passivation and thus long minority charge carrier lifetimes are achieved by deposition of intrinsic amorphous Si ((i) a-Si:H) layers. It is shown, that optimized (i) a-Si:H deposition parameters for planar Si (111) wafers can be transferred to a-Si:H layer deposition on random pyramid textured Si (100) wafers. Statistical analysis of the pyramid size distribution revealed that a low fraction of small pyramids leads to longer minority charge carrier lifetimes and, thus, a higher Voc potential for solar cells.