AOIO: Application Oriented I/O Optimization for Buffer Management

Emerging scale-out I/O intensive applications are broadly used now, which process a large amount of data in buffer/cache for reorganization or analysis and their performances are greatly affected by the speed of the I/O system. Efficient management scheme of the limited kernel buffer plays a key role in improving I/O system performance, such as caching hinted data for reuse in future, prefetching hinted data, and expelling data not to be accessed again from a buffer, which are called proactive mechanisms in buffer management. However, most of the existing buffer management schemes cannot identify data reference regularities (i.e., sequential or looping patterns) that can benefit proactive mechanisms, and they also cannot perform in the application level for managing specified applications. In this paper, we present an A pplication Oriented I/O Optimization (AOIO) technique automatically benefiting the kernel buffer/cache by exploring the I/O regularities of applications based on program counter technique. In our design, the input/output data and the looping pattern are in strict symmetry. According to AOIO, each application can provide more appropriate predictions to operating system which achieve significantly better accuracy than other buffer management schemes. The trace-driven simulation experiment results show that the hit ratios are improved by an average of 25.9% and the execution times are reduced by as much as 20.2% compared to other schemes for the workloads we used.

Konsep Managemen Memori

Konsep Dasar MemoriMemori adalah pusat dari operasi pada sistem komputer modern, berfungsi sebagai tempat penyimpanan informasi yang harus diatur dan dijaga sebaik-baiknya. Memori adalah array besar dari word atau byte, yang disebut alamat. CPU mengambil instruksi dari memory berdasarkan nilai dari program counter.

Konsep Managemen Memori (computer).

A. Manajemen MemoriKonsep Dasar MemoriMemori adalah pusat dari operasi pada sistem komputer modern, berfungsi sebagai tempat penyimpanan informasi yang harus diatur dan dijaga sebaik-baiknya. Memori adalah array besar dari word atau byte, yang disebut alamat. CPU mengambil instruksi dari memory berdasarkan nilai dari program counter.

PROGRAM KONTRA WACANA TERORISME: SEBUAH USULAN ANTROPOLOGIS SEBAGAI ALTERNATIF DERADIKALISASI DI INDONESIA

Program counter-discourse (kontra wacana) adalah program yang berusaha menciptakan “a way of thinking that opposes an institutionalized discourse”. Selama ini wacana kaum fundamentalis, kaum radikal hinga kelompok-kelompok teroris sudah terlembaga sedemikian rupa di Indonesia melalui proses yang panjang dalam sejarah sosial politik negeri ini. Teka-teki yang muncul atas motif apakah yang mendasari makin maraknya kaum profesional yang berkecukupan tergiur untuk menjadi tentara Negara Islam Irak dan Suriah (NIIS) atau yang lebih dikenal dengan ISIS (Islamic State of Iraq and Syria) belum juga terpecahkan secara komprehensif. Hingga saat ini, sudah sekitar 518 warga negara Indonesia diduga bergabung dengan ISIS dan menurut catatan Sidney Jones dari Institute for Policy Analysis of Conflict (IPAC), sudah lebih dari 800 warga negara Indonesia yang sudah berangkat dan bergabung dengan gerakan “teroris” tersebut di Suriah. Oleh karena itu, perlu membangun kontra wacana sebagai benteng untuk membendung upaya “cuci otak” yang dilakukan oleh pihak-pihak yang tidak bertanggung jawab. Program ini tentu saja tidak akan berjalan tanpa dukungan dari berbagai pihak terkait, terutama pihak-pihak yang paham dengan permasalahan ini. Padahal, di sisi lain, upaya dan program nyata untuk memerangi terorisme yang bersifat straight-forward dan sistematis seharusnya terus digalakkan dan terlembaga. Harapannya, program kontra wacana ini dapat mereduksi dan menghantam ideologi-ideologi yang menyimpang yang selama ini dianut oleh gerakan-gerakan sosial politik keagamaan.

A Computational Design of a Programmable Biological Processor

Basic synthetic information processing structures, such as logic gates, oscillators and flip-flops, have already been implemented in living organisms. Current implementations of these structures are, however, hardly scalable and are yet to be extended to more complex processing structures that would constitute a biological computer.Herein, we make a step forward towards the construction of a biological computer. We describe a model-based computational design of a biological processor, composed of an instruction memory containing a biological program, a program counter that is used to address this memory and a biological oscillator that triggers the execution of the next instruction in the memory. The described processor uses transcription and translation resources of the host cell to perform its operations and is able to sequentially execute a set of instructions written within the so-called instruction memory implemented with non-volatile DNA sequences. The addressing of the instruction memory is achieved with a biological implementation of the Johnson counter, which increases its state after an instruction is executed. We additionally describe the implementation of a biological compiler that compiles a sequence of human-readable instructions into ordinary differential equations-based models. These models can be used to simulate the dynamics of the proposed processor.The proposed implementation presents the first programmable biological processor that exploits cellular resources to execute the specified instructions. We demonstrate the application of the proposed processor on a set of simple yet scalable biological programs. Biological descriptions of these programs can be written manually or can be generated automatically with the employment of the provided compiler.

Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages

Many processors have evolved in the past century; Out of which, Reduced Instruction set Computing (RISC) processors are well known for their ease of use. The next in line was the Microprocessor without Interlocked pipelining stages (MIPS) RISC based architecture. Less number of instructions, good amount of registers makes these processors a boon to use. Often times, MIPS processors loose the battle against their contenders due to lack of speed. Hence, there is a sheer necessity in designing a more robust system that has all the advantages of MIPS. Over time, there have been designs that could solve the power drawbacks and the area optimizations. However, performance criterion is mostly neglected. This paper emphasizes on the performance metric of pipelined 32-bit MIPS microprocessor. This processor supports RISC architecture and has been designed under Harvard architecture. Pipelining technique is used to solve the problem of low performance and achieve smaller execution times. The processor has four pipes. Pipes are the structures which store data. Pipes can be viewed as register banks. These pipes are generally used to store the intermediate data. The design contains various modules like ALU, Instruction fetch register, Execution unit, Memory, Program counter (PC). Verilog HDL has been used to implement the design. The software used is Xilinx ISE for design and ISIM simulator has been used for simulation purposes. The applications of this MIPS microprocessor are abundant. MIPS microprocessor can be used to carry out the fundamental tasks and an application specific core/IP/processor can be designed and combined with MIPS. This facilitates in meeting the goals of high performance, lower time-to-market and cost- effectiveness. Some application specific uses can be for music systems, PDA, Image processing etc.

Design of Arm Processor’s Elements Using QCA

Quantum dot Cellular Automata is one of the promising future nano-technology for transistor-less computing which takes advantage of the coulomb force interacting between electrons. The aim of this paper is to consider the logical circuits of ARM processors and further reducing their size in nanometres like 2:1 multiplexer , D Flip Flop, scan Flip Flop, 2:1 multiplexer with enable, encoder, decoder, SR FF, shift register, memory cell and program counter are designed using QCAD tool . Their cell count, area, kink energy are taken in consideration to calculate power and energy dissipation.