scholarly journals Maximizing ATPG Diagnosis Resolution on Unique Single Failing Devices

2021 ◽  
Author(s):  
Andrew Sabate ◽  
Rommel Estores
Keyword(s):  
High Resolution ◽  
Failure Mechanism ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Isolation ◽  
Single Shot ◽  
Fault Type ◽  
Customer Returns ◽  
Diagnostic Resolution ◽  
Automatic Test Pattern Generator

Abstract Unique single failing device is common for customer returns and reliability failures. When the initial and iterative Automatic Test Pattern Generator (ATPG) could not provide a sufficient diagnostic resolution, it can become quite challenging for the analyst to determine the failure mechanism in an efficient and effective way. Fault isolation could be performed in combination with the diagnosis results but there are cases with mismatch between the results (location, fault type, suspect nets). When the diagnostic resolution is low, the probability for such mismatches are high. This paper proposes an approach to increase the diagnostic resolution by utilizing a high-resolution targeted pattern (HRT) and single shot logic (SSL) patterns. Two cases will be discussed in the paper to highlight this approach and show in detail how it was utilized on actual failing units.

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

scholarly journals Testability-Driven Layout of Combinational Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 347-352
Author(s):  
C. P. Ravikumar ◽  
Nikhil Sharma
Keyword(s):  
Test Generation ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Vector ◽  
Combinational Circuits ◽  
Bridging Faults ◽  
Cpu Time ◽  
On Line ◽  
Placement Algorithm ◽  
Automatic Test Pattern Generator

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

scholarly journals Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks

2020 ◽  
Vol 9 (2) ◽  
pp. 158
Author(s):  
Kurada Veera Bhoga Vasantha Rayudu ◽  
Jahagirdar Jahagirdar ◽  
P Rao
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Binary Decision Diagram ◽  
Basic Design ◽  
Modern Design ◽  
Ordered Binary Decision Diagram ◽  
Binary Decision ◽  
Toggling Faults ◽  
The Individual ◽  
Automatic Test Pattern Generator

In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

scholarly journals Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python

2021 ◽  
Vol 23 (06) ◽  
pp. 530-536
Author(s):  
Mahesh Bhat K ◽  
◽  
Namita Palecha ◽  
Keyword(s):  
Test Pattern ◽  
Fault Simulation ◽  
Pattern Generator ◽  
Channel Length ◽  
Simulation System ◽  
Hardware Accelerator ◽  
Vlsi Testing ◽  
Automatic Test Pattern Generator ◽  
Test Vectors ◽  
Input Test

VLSI Testing is one of the essential domains in recent times. With the channel length of the transistor decreasing continually, the number of transistors in a chip increases, thus increasing the probability of defects or faults. Automatic Test Pattern Generator is one way to find such input test vectors to the circuit, which will help identify the faults if present. PODEM algorithm is one such algorithm used in this regard. This paper helps in reducing the runtime of this algorithm by the parallelism approach. Different stuck-at faults in the gate level circuit are simulated parallelly.

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