Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks

Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.

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Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽

10.3390/electronics10040516 ◽

2021 ◽

Vol 10 (4) ◽

pp. 516

Author(s):

Tram Thi Bao Nguyen ◽

Tuy Nguyen Tan ◽

Hanho Lee

Keyword(s):

Wireless Communication ◽

High Throughput ◽

Low Complexity ◽

Ldpc Decoder ◽

Processor Architectures ◽

New Radio ◽

Decoder Architecture ◽

Check Node ◽

Information Update ◽

Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

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Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.241-244.2457 ◽

2012 ◽

Vol 241-244 ◽

pp. 2457-2461 ◽

Cited By ~ 2

Author(s):

Murali Maheswari ◽

Gopalakrishnan Seetharaman

Keyword(s):

Error Correction ◽

Error Rate ◽

Iterative Decoding ◽

Error Control ◽

Low Complexity ◽

Hardware Complexity ◽

Error Correction Coding ◽

Product Code ◽

Coding Scheme ◽

On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

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Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding

2018 International Conference on Advanced Technologies for Communications (ATC) ◽

10.1109/atc.2018.8587443 ◽

2018 ◽

Author(s):

Huyen Pham Thi ◽

Hung Dao Tuan ◽

Le Dinh Trang Dang ◽

Hanho Lee ◽

Tho Nguyen Huu

Keyword(s):

Low Complexity ◽

Ldpc Decoding ◽

Check Node

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Hybrid Decoding Algorithm for LDPC Codes with Circles

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.271-273.258 ◽

2011 ◽

Vol 271-273 ◽

pp. 258-263

Author(s):

Li Shuang Hu ◽

Ming Shan Liu ◽

Yuan Zhou ◽

Yang Sun

Keyword(s):

Error Rate ◽

Belief Propagation ◽

Additive White Gaussian Noise ◽

Ldpc Codes ◽

Error Correcting Codes ◽

Parity Check ◽

Likelihood Ratios ◽

Decoding Algorithms ◽

Variable Node ◽

Check Node

At present, Low-Density Parity-Check (LDPC) codes widely used in many fields of communications have the best performance of all the Error Correcting Codes (ECC). This paper mainly studies the decoding algorithms of LDPC. It proposes an improved algorithm which is named Check-Variable nodes Hybrid(CVH) algorithm on the basis of the existing algorithms. The CVH algorithm can reduce the computational complexity during the check-node update while overcome with the correlation between the variable-node news in a code with circles. As well as, comparing with the original algorithms the performance of the new one saves 0.1 and 0.3 dB than Log-likelihood Ratios (LLR) Belief Propagation (BP) and BP - based algorithms under Additive White Gaussian Noise (AWGN) channel when the Bit Error Rate (BER) falls to through the simulation. This point shows that this algorithm can increase the decoding performance and reduce the error rate effectively.

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Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme

Journal of Circuits System and Computers ◽

10.1142/s0218126617500281 ◽

2016 ◽

Vol 26 (02) ◽

pp. 1750028

Author(s):

Cheng-Hung Lin ◽

Tzu-Hsuan Huang ◽

Shu-Yen Lin ◽

Yu-Hsuan Lee

Keyword(s):

Power Dissipation ◽

Message Passing ◽

Cmos Process ◽

Two Phase ◽

Ldpc Decoder ◽

Design And Implementation ◽

Ldpc Decoding ◽

Area Overhead ◽

Check Node ◽

Decoder Design

In this paper, we propose an operation-reduced low-density parity check (LDPC) decoder design and implementation by stopping reliable operation of check nodes of the iterative two-phase message passing (TPMP) min-sum algorithm (MSA). A check node stopping (CNS) scheme is used to tag reliability of check nodes by detecting the magnitudes of the check node belief messages with a threshold. The operation of reliable check nodes tagged by the CNS scheme can be stopped in the later iterations. The proposed LDPC decoder that employs the CNS scheme can significantly terminate the redundant operations of check nodes and efficiently reduce the power consumption of decoder. From the simulations under WiMAX QC LDPC decoding with high channel quality, the CNS scheme achieves up to 12% stopping rate of check nodes with a loss of coding gain less than 0.1 dB. The WiMAX QC LDPC decoder chip that employs the CNS scheme is implemented by a 90-nm CMOS process. Compared with the LDPC decoder that employs no CNS scheme, the overall power dissipation of the proposed LDPC decoder is decreased by 4.1% with 0.5% area overhead.

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5G Systems with Low Density Parity Check based Chanel Coding for Enhanced Mobile Broadband Scheme

March 2019 - IRO Journal on Sustainable Wireless Systems ◽

10.36548/jsws.2020.1.005 ◽

2020 ◽

Vol 2 (1) ◽

pp. 42-49 ◽

Cited By ~ 1

Author(s):

Dr. Joy Iong Zong Chen

Keyword(s):

Error Rate ◽

Turbo Codes ◽

Additive White Gaussian Noise ◽

Low Complexity ◽

Polar Codes ◽

Low Density ◽

Parity Check ◽

Mobile Broadband ◽

Coding Schemes ◽

Low Density Parity Check

The 5G mobile communication standard based radio access technology (RAT) is analysed for implementation of several candidate coding schemes in this paper. The third generation partnership project (3GPP) in the 5G scenario based on the Enhanced mobile broadband (eMBB) scheme is considered. Factors like flexibility, complexity of computation, bit error rate (BER), and block error rate (BLER) are considered for the purpose of evaluation of the coding schemes. In order to evaluate the performance various applications and services, a suitable set is of parameters are provided. The candidate schemes considered for this purpose are polar codes, low density parity check (LDPC) and turbo codes. Fair comparison is performed by investigation of block lengths and obtaining suitable rates by proper design. In an additive white Gaussian noise (AWGN) channel, the performance of BLER / BER is obtained for diverse block lengths and code rates based on simulation. The simulation results show that the performance of LDPC is relatively efficient for various code rates and block lengths despite the better performance of polar codes at short block lengths. As an added advantage, LDPC codes also offer relatively low complexity.

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Graph-Based Detection and LDPC Decoding over 2D Intersymbol Interference Channels

Journal of Communications ◽

10.12720/jcm.16.3.91-98 ◽

2021 ◽

pp. 91-98

Author(s):

Yingying Li ◽

◽

Zhiliang Qin ◽

Lianghui Zou ◽

Yu Qin ◽

...

Keyword(s):

Intersymbol Interference ◽

Iterative Detection ◽

Interference Channels ◽

Parity Check ◽

Ldpc Decoder ◽

Ldpc Decoding ◽

Low Density Parity Check ◽

Iterative Detection And Decoding ◽

Check Node ◽

Isi Channels

In this paper, we propose a fully graph-based iterative detection and decoding scheme for Low-Density Parity-Check (LDPC) coded generalized two-dimensional (2D) intersymbol interference (ISI) channels. The 2D detector consists of a downtrack detector based on the symbol-level sum-product algorithm (SPA) and a bit-level SPA-based crosstrack detector. A LDPC decoder based on simplified check node operations is also proposed to provide soft information for the 2D channel detector. Numerical results show that the proposed receiver achieves better performance as compared with the trellis-based BCJR detector over 2×2 2D channels while at a significantly lower computational complexity.

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