scholarly journals Reduced Area and Low Power Implementation of FFT/IFFT Processor

2018 ◽  
Vol 14 (2) ◽  
pp. 108-119 ◽  
Author(s):  
Shefa Dawwd ◽  
Suha Nori
Keyword(s):  
Fixed Point ◽  
Shared Memory ◽  
Digital Signal ◽  
Processing Unit ◽  
Memory Location ◽  
Hardware Cost ◽  
System Generator ◽  
Place Memory ◽  
Input Sample ◽  
Memory Scheme

The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.

scholarly journals An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
Cheng C. Wang ◽  
Changchun Shi ◽  
Robert W. Brodersen ◽  
Dejan Marković
Keyword(s):  
Fixed Point ◽  
Low Power ◽  
High Performance ◽  
Floating Point ◽  
View Point ◽  
Hardware Cost ◽  
System Generator ◽  
Area Estimation ◽  
Complex Optimization ◽  
Automated Tool

This paper presents an automated tool for floating-point to fixed-point conversion. The tool is based on previous work that was built in MATLAB/Simulink environment and Xilinx System Generator support. The tool is now extended to include Synplify DSP blocksets in a seamless way from the users' view point. In addition to FPGA area estimation, the tool now also includes ASIC area estimation for end-users who choose the ASIC flow. The tool minimizes hardware cost subject to mean-squared quantization error (MSE) constraints. To obtain more accurate ASIC area estimations with synthesized results, 3 performance levels are available to choose from, suitable for high-performance, typical, or low-power applications. The use of the tool is first illustrated on an FIR filter to achieve over 50% area savings for MSE specification of 10−6 as compared to all 16-bit realization. More complex optimization results for chip-level designs are also demonstrated.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

Adaptive Control for Buck Power Converter Using Fixed Point Inducting Control and Zero Average Dynamics Strategies

2015 ◽  
Vol 25 (04) ◽  
pp. 1550049 ◽  
Author(s):  
Fredy Edimer Hoyos Velasco ◽  
Nicolás Toro García ◽  
Yeison Alberto Garcés Gómez
Keyword(s):  
Fixed Point ◽  
Digital Signal ◽  
Power Converter ◽  
Buck Converter ◽  
Control Techniques ◽  
Comparison Results ◽  
Control Scheme ◽  
Rapid Control ◽  
Rapid Control Prototyping ◽  
Lms Method

In this paper, the output voltage of a buck power converter is controlled by means of a quasi-sliding scheme. The Fixed Point Inducting Control (FPIC) technique is used for the control design, based on the Zero Average Dynamics (ZAD) strategy, including load estimation by means of the Least Mean Squares (LMS) method. The control scheme is tested in a Rapid Control Prototyping (RCP) system based on Digital Signal Processing (DSP) for dSPACE platform. The closed loop system shows adequate performance. The experimental and simulation results match. The main contribution of this paper is to introduce the load estimator by means of LMS, to make ZAD and FPIC control feasible in load variation conditions. In addition, comparison results for controlled buck converter with SMC, PID and ZAD–FPIC control techniques are shown.

scholarly journals Fixed Point Implementation of Grid Tied Inverter in Digital Signal Processing Controller

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 89215-89227 ◽  
Author(s):  
Shuvangkar Shuvo ◽  
Eklas Hossain ◽  
Ziaur Rahman Khan
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Digital Signal Processing ◽  
Digital Signal
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