scholarly journals Pair Wise Swapping Based Hypergraph Partitioning Algorithms for VLSI Design

2019 ◽  
Vol 8 (2) ◽  
pp. 5589-5593
Keyword(s):  
Integrated Circuit ◽  
Digital Camera ◽  
Vlsi Design ◽  
Electronic Systems ◽  
Circuit Partitioning ◽  
Computing Device ◽  
Hypergraph Partitioning ◽  
Vlsi Physical Design ◽  
Portable Computing ◽  
Partitioning Algorithms

A VLSI integrated circuit is the most significant part of electronic systems such as personal computer or workstation, digital camera, cell phone or a portable computing device, and automobile. So development within the field of electronic space depends on the design planning of VLSI integrated circuit. Circuit partitioning is most important step in VLSI physical design process. Many heuristic partitioning algorithms are proposed for this problem. The first heuristic algorithm for hypergraph partitioning in the domain of VLSI is FM algorithm. In this paper, I have proposed three variations of FM algorithm by utilizing pair insightful swapping strategies. I have played out a relative investigation of FM and my proposed algorithms utilizing two datasets for example ISPD98 and ISPD99. Test results demonstrate that my proposed calculations outflank the FM algorithm.

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Application

2020 ◽  
Vol 18 (1) ◽  
pp. 31-38
Author(s):  
Vivek Pogra ◽  
Santosh Kumar Vishvakarma ◽  
Balwinder Raj
Keyword(s):  
Internet Of Things ◽  
Integrated Circuit ◽  
Direct Memory Access ◽  
Electronic Systems ◽  
Memory Module ◽  
Iot Platform ◽  
Application Specific Integrated Circuit ◽  
And Performance ◽  
Application Specific ◽  
Novel Design

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the Internet. The transfer of data between different networks and internet of things (IoT) platform is controlled by IoT platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to the fact that it is designed for IoT applications. It is described in VHDL at RTL level and simulation is done on the Vivado 2016.2.

scholarly journals A enhanced algorithm for floorplan design using evolutionary technique

2012 ◽  
Vol 1 (2) ◽  
pp. 38
Author(s):  
Dhiraj Dhiraj ◽  
Seema Verma ◽  
Rajesh Kumar ◽  
Himanshu Choudhary
Keyword(s):  
Integrated Circuit ◽  
Design Automation ◽  
Large Scale ◽  
Vlsi Design ◽  
Optimal Placement ◽  
Iterative Approach ◽  
Modified Genetic Algorithm ◽  
Evolutionary Technique ◽  
Floor Planning

Floor planning is an important problem in very large scale integrated-circuit (VLSI) design automation domain as it evaluates the performance, size, yield and reliability of ICs. Due to rapid increase in number of components on a chip, floor planning has gained its importance further in determining the quality of the design achieved. In this paper we have devised an approach for placement of modules in a given area with bounding constraints in terms of minimum placement area imposed. We have used Modified Genetic Algorithm (MGA) technique for determining and obtaining an optimal placement using an iterative approach.

VLSI Design at the Undergraduate Level

1987 ◽  
Vol 24 (4) ◽  
pp. 309-318 ◽  
Author(s):  
J. G. Swanson
Keyword(s):  
Integrated Circuit ◽  
Vlsi Design ◽  
Undergraduate Level ◽  
Cmos Integrated Circuit ◽  
Electronic Engineering ◽  
Academic Year

This paper describes the experience gained in teaching a VLSI design course to students in the final year of a three-year course in Electronic Engineering. Each of the twenty students designed and tested their own full-custom CMOS integrated circuit within one academic year.

scholarly journals A Trusted Portable Computing Device

2012 ◽  
Vol 25 ◽  
pp. 1027-1033
Author(s):  
Fang Ming-wei ◽  
Wu Jun-jun ◽  
Yu Peng-fei ◽  
Zhang Xin-fang
Keyword(s):  
Computing Device ◽  
Portable Computing

The Development of an Undergraduate Curriculum for VLSI Design

1989 ◽  
Vol 26 (1-2) ◽  
pp. 11-17
Author(s):  
R. E. Massara ◽  
A. D. P. Green ◽  
R. J. Mack ◽  
P. D. Noakes
Keyword(s):  
Vlsi Design ◽  
Systems Design ◽  
Undergraduate Curriculum ◽  
Laboratory Work ◽  
Electronic Systems ◽  
Ic Design ◽  
Chip Fabrication ◽  
Core Course ◽  
Circuit Technology ◽  
Technology And Design

This contribution describes the way in which the ECAD facilities have been exploited in the development of an undergraduate curriculum for the teaching of IC design in an Electronic Systems B. Eng. degree scheme. The programme of course and laboratory work culminates in a final year core course in Microelectronic Circuit Technology and Design together with a specialist option in VLSI Systems Design which includes chip fabrication activities.

Amorphous Silicon Electronics

MRS Bulletin ◽  
1992 ◽  
Vol 17 (11) ◽  
pp. 70-76 ◽  
Author(s):  
R.A. Street
Keyword(s):  
Information Technology ◽  
Amorphous Silicon ◽  
Integrated Circuit ◽  
Electronic Systems ◽  
Large Format ◽  
Computing Power ◽  
Physical Size ◽  
Interactive Display ◽  
Machine Communication ◽  
Portable Computers

The progressive miniaturization of electronics is familiar to everyone; computing power that used to occupy a room can now be put onto a single integrated circuit. Miniaturization is admirable when size is not relevent to the electronic function, but there are plenty of devices in which a large physical size is essential. Many of these concern information technology, examples being the computer display, printer, and fax machine. Communication with the electronic world is primarily visual and operates at a large format typified by a document. In this rapidly advancing field, we are eagerly awaiting desktop interactive display surfaces that can input as well as display information, document readers, truly portable computers, electronic vision and—the oldest dream of all—the television that hangs on the wall. Realization of these hopes requires a set of technologies that permit bigger rather than smaller electronic systems, and amorphous silicon is helping to make this happen.

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